Tohru Ishihara

A built-in self-adjustment scheme with adaptive body bias using P/N-sensitive digital monitor circuits

This paper proposes a built-in self-adjustment scheme to adjust pMOSFET and nMOSFET performances to their target values. Independent control of MOSFET performances can boost circuit performance without large leakage overhead. All-digital monitor circuits have been developed to detect pMOSFET and nMOSFET variations. The scheme has been fabricated in a 65 nm process. Measurement results from corner chips confirm the validity of the scheme. At 0.7 V operation, more than 50% of circuit speed degradation has been recovered. The proposed scheme achieves 2.6 times leakage saving than the conventional critical path delay based scheme. The scheme is suitable for typical-case design and yield enhancement.

Reconfigurable delay cell for area-efficient implementation of on-chip MOSFET monitor schemes

To measure target MOSFET variation, specific monitor schemes are required. With device scaling, developing each monitor scheme is costly. This paper proposes a universal delay monitor cell which enables measurements of various types of variations with single monitor scheme. The monitor cell is reconfigurable and standard cell compatible; thus it can be used in the conventional place and route flow. An area-efficient monitor scheme to monitor global, local, and dynamic variations is developed. Measurement results from a 65-nm test chip shows the validity of the proposed monitor cell. The proposed cell enables area-efficient and low cost implementation of monitor schemes which can be integrated with application such as testing and adaptive voltage scaling.

Analysis and comparison of XOR cell structures for low voltage circuit design

The performance of standard cells has a strong impact on the performance of a circuit synthesized with the cells. Although a complementary CMOS logic is usually used in the standard cells, it is known that a pass transistor logic can improve the performance of a circuit with a smaller area in some cases. We evaluate different types of XOR cells in different voltage conditions. Results show that the dual pass transistor XOR has a better performance than the complementary CMOS XOR in 0.6V operation, while the complementary CMOS XOR has a better performance in 1.2 V operation. More specifically, the area and the power consumption of a benchmark circuit composed of the dual pass transistor XOR can be reduced by 24% and 35%, respectively, compared to those of the same circuit composed of the complementary CMOS XOR in 0.6V operation.

Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems

This paper proposes a task scheduling approach for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable SRAMs under real-time constraints. A mixed integer programming model has been built for minimizing vulnerability under real-time constraints. Experimental results have shown that our task scheduling approach achieved 47.7-99.9% less vulnerability than a conventional one.

Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems

This paper proposes a soft-error model for accurately estimating reliability of a computer system at the architectural level within reasonable computation time. The architectural-level soft-error model identifies which part of memory modules are utilized temporally and spatially and which single event upsets (SEUs) are critical to the program execution of the computer system at the cycle accurate instruction set simulation (ISS) level. The soft-error model is capable of estimating reliability of a computer system that has several memory hierarchies with it and finding which memory module is vulnerable in the computer system. Reliability estimation helps system designers apply reliable design techniques to vulnerable part of their design. The experimental results have shown that the usage of the soft-error model achieved more accurate reliability estimation than conventional approaches. The experimental results demonstrate that reliability of computer systems depends on not only soft error rates (SERs) of memories but also the behavior of software running in computer systems.

An energy-efficient on-chip memory structure for variability-aware near-threshold operation

On-chip memory is one of the most energy consuming components in processors. Aggressive voltage scaling to the sub-/near-threshold region is thus applied even to the memory used for ultra-low power applications. In this paper, an energy-efficient cell-based memory structure which is stably working with a near-threshold operating voltage is proposed. The circuit simulation using a commercial 28-nm technology shows that the energy consumption for the readout operation in our memory proposed here is up to 61% less than the energy dissipated in an existing cell-based memory and a conventional SRAM circuit. The simulation using a foundry provided Monte Carlo package also shows that the 3σ worst case read-access time of our cell-based memory is comparable to that of the SRAM circuit.

Brillouin Scattering in Densified GeO2 Glasses.

Brillouin and Raman scattering measurements have been applied for the investigation of GeO2 glasses densified under high pressures up to 9 GPa at 673 K. The density of obtained glasses increases with an increase of applied pressure. It increases significantly around 3 GPa, however, shows a peak at 6 GPa. A significant increase is also observed in hypersonic wave velocity, and longitudinal and shear moduli around 3 GPa. These results are well explained by amorphous-amorphous transition. In Raman scattering measurement, vibrational modes illustrate continuous changes of local structures with increasing applied pressures up to 9 GPa. Boson peaks show a maximum around 3 GPa, which indicates the minimum correlation length. These data suggest a change in the intermediate-range structure.

Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories

Memory accesses are a major cause of energy consumption for embedded systems and the stack is a frequent target for data accesses. This paper presents a fully software technique which aims at reducing the energy consumption related to the stack by allocating and transferring frames or part of frames between a scratch-pad memory and the main memory. The technique utilizes an integer linear formulation of the problem in order to find at compile time the optimal management for the frames. The technique is also extended to integrate existing methods which deal with static memory objects and others which deal with recursive functions. Experimental results show that our technique effectively exploits an available scratch-pad memory space which is only one half of what the stack requires to reduce the stack-related energy consumption by more than 90% for several applications and on an average of 84% compared to the case where all the frames of the stack are placed into the main memory.

Flexible System LSI for Embedded Systems and Its Optimization Techniques

In this paper, we propose a chip architecture and design techniques to simultaneously reduce both the chip cost and power consumption of system-on-a-chip (SOCs). The chip cost of SOCs consists of the design cost, the mask cost, the fabrication cost, the package cost, and the test cost. In case that the production volume of one design is large, the fabrication cost becomes relatively larger than other costs. The minimization of the fabrication cost by shrinking the chip area has been the main problem to reduce the chip cost. SOCs are not always mass-produced and their design and the mask costs are dominant. We need new design criteria and a new design methodology for SOCs whose production volume is small. Our major contribution is a proposal of a design methodology based on new criteria suitable for SOC design. In our methodology, system designers use a pre-fabricated chip, called Flexible System LSI (FlexSys) chip, which consists of a processor, memories, and other cores specific to an application domain. At the fabrication phase, the power supply for unused parts of the FlexSys chip is cut off using a few additional masks which are designed for a specific application. This leads the reduction of wasteful power consumed by circuits which do not essentially contribute to the computation of the application. Since the basic die of the FlexSys is fabricated as a general purpose product, we can reduce the cost of the dies drastically. Experimental results show that about 30% power reduction can be achieved without performance loss by reducing the wasteful power consumption.

Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing

This paper proposes a standard-cell based memory (SCM) as an alternative to a traditional on-chip SRAM for near-threshold voltage computing. It focuses on area- and energy-efficiency using minimum height standard-cells. Unlike conventional SCMs, the proposed SCM has standard-cells with a minimum possible cell height allowed by the logic design rule of the target technology. This paper also presents energy efficient readout and write schemes for reducing dynamic energy consumption. Post layout simulation using 65-nm FDSOI technology shows that the proposed SCM achieves area efficiency of 5.9 μm2 per bit (592F2 per bit), which is less than that of the state of the art SCMs. The results also show that the energy consumption is further improved when the supply voltage scaling and back-gate biasing techniques are applied to our SCM.