Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Hidenaga Takahashi is active.

Publication


Featured researches published by Hidenaga Takahashi.


international conference on consumer electronics | 1992

Development and architecture of second generation 6 chip MUSE (HDTV) decoder

Kiyoshi Kohiyama; Mitsuhiko Ohta; Hidenaga Takahashi; Kiyotaka Ogawa; Yukio Otobe; Masanori Kurita; Fumitaka Asami; N. Tahara; Koui Sugihara

The architecture of a six-chip MUSE (HDTV) LSI family which decodes MUSE video and audio signals is presented. With this architecture, the number of components can be reduced to a fifth of former levels. Because entire MUSE functions were integrated entirely onto the chips, improvements of various functions can be made chip by chip, ensuring a long life span for the LSI family as a whole. >


international conference on consumer electronics | 2001

A single-chip MPEG2 MP@HL decoder for DTV recording/playback systems

Yasuhiro Watanabe; Yukio Otobe; K. Yoshitomi; Hidenaga Takahashi; Kiyoshi Kohiyama

This paper presents an MPEG2 MP@HL decoder LSI for use in digital TV (DTV) recording/playback systems such as a home server. It integrates the functions required in home servers on a single chip. The chip incorporates not only basic functions for image processing but also effective functions for stream recording/playback. It enables smooth execution of trick plays without complex operations in an external CPU, and makes it easy to build recording/playback systems.


international conference on consumer electronics | 1994

Development of low operating voltage 2.5th generation MUSE (HDTV) chip set

Kouta Ohtsubo; Hidenaga Takahashi; Kiyotaka Ogawa; Kiyoshi Kohiyama; Tetsuo Aoki

In 1992 we developed a 2nd generation MUSE chip set containing more than 4.2 million transistors (five video chips and one audio chip). The chip set reduced the number of components to about 115, and power to about 113 compared with older first-generation chip sets. As a result, the cost of the HDTV (MUSE) receiver was cut by about 50%. But demand for even less expensive HDTV (MUSE) receivers is strong. We describe the development of a 2.5th generation MUSE chip set which through reduction of the operating voltages we succeeded in a 50% reduction in power consumption, and a 40% reduction in cost while maintaining compatibility with previous 2nd generation LSIs. >


international conference on consumer electronics | 1995

Considerations for system development of one-chip video MUSE (HDTV) decoder

Hidenaga Takahashi; K. Otsubo; H. Nagata; Kiyoshi Kohiyama; Gensuke Goto; T. Aoki; F. Asami

This paper describes system considerations in the development of a 3rd generation MUSE, video signal decoder implemented on a single chip. We achieved low cost while improving picture quality through cost effective improvements in the moving picture filter and through development of special interfacing circuitry which made it possible to use low cost general purpose synchronous DRAMs instead of customized FIFO DRAMs. >


international conference on consumer electronics | 1993

Development and conditions of an HDTV multimedia system

Yukio Otobe; Mitsuhiko Ohta; Hidenaga Takahashi; Kiyotaka Ogawa; Nobuyuki Tanaka; Kiyoshi Kohiyama

The development of an HDTV (high-definition television) multimedia system for use in home information terminals is described. It displays multiple incompatible images, such as MUSE (multiple sub-Nyquist sampling encoding), NTSC (National Television System Committee), and CG (computer graphics), on the same screen at the same time. It records the created, processed, or displayed images. High-quality MUSE images can be converted to NTSC images and recorded on conventional VCRs. Display interfaces are provided for various display units used in personal computers and in the NTSC system. The use of optimized chip sets makes the system compact and inexpensive, solving the problems of cost, size, and compatibility. >


Archive | 2007

Memory device, memory controller and memory system

Tomohiro Kawakubo; Syusaku Yamaguchi; Hitoshi Ikeda; Toshiya Uchida; Hiroyuki Kobayashi; Tatsuya Kanda; Yoshinobu Yamamoto; Satoru Shirakawa; Tetsuo Miyamoto; Tatsushi Otsuka; Hidenaga Takahashi; Masanori Kurita; Shinnosuke Kamata; Ayako Sato


Archive | 1991

One-chip first-in first-out memory device having matched write and read operations

Kiyoshi Kohiyama; Hidenaga Takahashi; Yukio Otobe


Archive | 1989

Color image display control apparatus with correction of phase difference in sampling clock

Kiyoshi Kohiyama; Shozo Kobatake; Hidenaga Takahashi


Archive | 1989

Method and apparatus for detecting a phase difference between two digital signals

Kiyoshi Kohiyama; Hidenaga Takahashi


Archive | 1999

METHOD AND DEVICE FOR DECODING MOVING PICTURE

Kiyoshi Kohiyama; Yukio Otobe; Hidenaga Takahashi; Koji Yoshitomi

Collaboration


Dive into the Hidenaga Takahashi's collaboration.

Researchain Logo
Decentralizing Knowledge