N. Tahara

A single-chip CMOS analog/digital mixed NTSC decoder

A CMOS LSI that integrates all analog-to-digital (A/D) and digital-to-analog (D/A) circuits, digital signal-processing circuits, and peripherals necessary for a digital NTSC (National Television System Committee) signal decoder on a single chip is described. The chip accepts composite NTSC signals in analog form, digitizes them, converts them to component RGB signals by digital signal processing, and changes the signals to analog form using the on-chip D/As. The key to making the single chip possible is the development of circuits which maximize utilization of the input digital data so that acceptable picture quality can be maintained despite 6-b resolution. Thus a 6-b A/D can be used, resulting in reduced circuit size.<<ETX>>

Development of a digital TV system for use in computer systems

The authors have developed a digital TV system and LSIs which are expected to act as a bridge between the computer-generated image and the TV picture. These LSIs make possible the development of a system that can display TV pictures and computer-generated images simultaneously on a personal computer or workstation monitors. This system is expected to play an important part in desktop video systems. The monitor of the personal computer displays the computer and TV images at the same time. >

Development and architecture of second generation 6 chip MUSE (HDTV) decoder

The architecture of a six-chip MUSE (HDTV) LSI family which decodes MUSE video and audio signals is presented. With this architecture, the number of components can be reduced to a fifth of former levels. Because entire MUSE functions were integrated entirely onto the chips, improvements of various functions can be made chip by chip, ensuring a long life span for the LSI family as a whole. >

A multipurpose single chip JBIG based compression/decompression system

The Joint Bilevel Image Experts Group (JBIG) coding system was adopted as an international standard for next-generation image coding systems. An LSI which compresses/decompresses images 1-pixel/clock through pipeline architecture and conforms to JBIG and conventional modified Huffman/modified read/modified modified read (MH/MR/MMR) coding functions and has flexible bus configuration facilities to allow multipurpose use is described.