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Dive into the research topics where Hidenobu Fukutome is active.

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Featured researches published by Hidenobu Fukutome.


Applied Surface Science | 1998

Scanning tunneling microscopy study of the hydrogen-terminated n- and p-type Si(001) surfaces

Hidenobu Fukutome; Keizo Takano; Haruyuki Yasuda; Kenzo Maehashi; Shigehiko Hasegawa; Hisao Nakashima

Abstract We have investigated hydrogen-passivated Si(001) surfaces with various doping conditions using X-ray photoelectron spectroscopy (XPS), scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS). It is found that Si 2 p peak energies of XPS for the hydrogen-passivated surfaces depend on the doping conditions while Si 2 p XPS peaks for reconstructed surfaces after annealing them at 700°C always have the same binding energies without depending on the doping conditions. This suggests that the surface Fermi level on the hydrogen-passivated Si(001) surface is unpinned. STM/STS measurements reveal that a shoulder originating from a dopant level exists in the current–voltage ( I – V ) curve obtained by STS. We discuss the possibility to obtain bulk electronic characteristics of Si through its hydrogen-passivated surface with the use of STM/STS.


Journal of Vacuum Science & Technology B | 2004

Two-dimensional characterization of carrier concentration in metal-oxide-semiconductor field-effect transistors with the use of scanning tunneling microscopy

Hidenobu Fukutome; Hiroshi Arimoto; Shigehiko Hasegawa; Hisao Nakashima

An evaluation technique for two-dimensional (2D) carrier profiles in metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented that is based on the use of scanning tunneling microscopy (STM). First, the procedure of STM-based carrier profiling method is presented. Sample preparation that enables accurate carrier measurements is described. It is shown that STM has both the spatial resolution and sensitivity of tunneling current to carrier concentration enough to evaluate the carrier profile in an aggressively scaled device. The conversion method from obtained images into carrier profiles is described. Next, the STM-based technique is used to evaluate two-dimensional carrier profiles in the extension regions of 70 nm n-MOSFETs. The dependence of 2D carrier profiles in the extension regions where arsenic is implanted at an energy of 3 keV on the implantation dose and annealing temperature is investigated. STM is a powerful tool for the efficient development of scaled Si devices.


Applied Surface Science | 1999

Visualization of the depleted layer in nanoscaled pn junctions on Si(001) surfaces with the use of scanning tunneling microscopy

Hidenobu Fukutome; Shigehiko Hasegawa; Keizo Takano; Hisao Nakashima; Takayuki Aoyama; Hiroshi Arimoto

Abstract We demonstrate that the microscopic variation of the bulk electronic properties of nanoscaled pn junctions formed on Si(001) surface is clearly visualized with the use of scanning tunneling microscopy/scanning tunneling spectroscopy (STM/STS). The STM measurement reveals that it is possible to distinguish among the n-type the p-type and the depleted p-type regions. It is shown that the contrasts between the regions strongly depend on the bias voltage for the STM measurement. Especially, for the negative sample bias voltage, it is observed that the width of the depletion layer gets wider with decreasing the sample bias voltage. We will discuss the origin of the bias voltage dependence of the STM image in terms of a metal–insulator–semiconductor structure model. It is also shown that the current imaging tunneling spectroscopy image can also visualize three regions of the nanoscaled pn junctions.


Japanese Journal of Applied Physics | 2004

Characterization of Plasma Nitridation Impact on Lateral Extension Profile in 50 nm N-MOSFET by Scanning Tunneling Microscopy

Hidenobu Fukutome; Takashi Saiki; Mitsuaki Hori; Takuji Tanaka; Ryou Nakamura; Hiroshi Arimoto

The electrical performances of sub-50-nm n-metal-oxide-semiconductor field effect transistors (n-MOSFETs) are improved when a plasma nitridation process is used after the gate electrodes are formed. The maximum drive current is increased by 2% and the minimum gate length is shrunk by 5% while the off-leakage current is maintained. Inverse modeling suggested that these improvements were due to nitridation-induced changes in the two-dimensional carrier profile, and scanning tunneling microscopy confirmed that they were. The plasma nitridation decreased the overlapping length from 12 nm to 10 nm and increased the steepness of the lateral abruptness of the extension region from 3.6 nm/decade to 1.8 nm/decade. Such an optimized profile is thought to be mainly due to nitrogen suppressing the lateral anomalous diffusion of the arsenic piled-up along the interface between the silicon substrate and the insulating layer.


Solid-state Electronics | 1998

Direct imaging of nano pn junctions and their bulk electronic properties with the use of scanning tunneling microscopy

Hidenobu Fukutome; Keizo Takano; Shigehiko Hasegawa; Hisao Nakashima; Takayuki Aoyama; Hiroshi Arimoto

Abstract We have investigated the nanoscaled pn junctions formed by As implantation on the p-type Si(001) surface with the use of scanning tunneling microscopy (STM). The STM measurement reveals that the contrast of the alternating bright and dark lines corresponding to the planar pn junctions strongly depends on the bias voltage. The origin of the observed contrasts depending on bias voltages is discussed in terms of a model of a metal–insulator–semiconductor structure combined with pn junctions.


Surface Science | 2000

Shearing orientation dependence of cleavage step structures on GaAs(110)

Toshiko Okui; Shigehiko Hasegawa; Hidenobu Fukutome; Hisao Nakashima

Abstract Scanning tunneling microscopy has been used to evaluate surface roughness and step structures of cleaved GaAs(110) surfaces. It is found that they are dependent on the direction of the force applied during cleaving. The flattest surface having fairly straight [110]-type steps is obtained when cleaving samples toward the [110] direction. Cleaving samples toward [001] also leads to smooth surfaces with [001]-, [112]-, and/or [114]-type steps. In contrast, when cleaving samples toward [112] or [114], the surfaces obtained have many fluctuated atomic steps. We will discuss the observed shearing orientation dependence of the cleavage step structures in terms of configurations of AsGa bonds.


Japanese Journal of Applied Physics | 2010

Sub-30-nm Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with Pt-Incorporated Fully Ni-Silicide/SiON Gate Stack

Hidenobu Fukutome; Kazuya Okubo; Shinichi Akiyama; Naoki Idani; Hiroyuki Ohta; Kazuo Kawamura; Yoichi Momiyama; Shigeo Satoh

We demonstrated an ideal scaling of inversion gate dielectric thickness (Tinv) without the decrease in the channel strain of a short-channel planar transistor using a Pt-incorporated fully Ni-silicide (Ni-FUSI)/SiON gate stack. We have achieved drive currents of 1.1/0.65 mA/µm at an off-leakage current of 50 nA/µm for the sub-30-nm n- and p-metal–oxide–semiconductor field effect transistors (MOSFETs). Because the decrease in gate length was larger than the Tinv scaling while maintaining a high drive current, the Ni-FUSI/SiON gate stack improved the intrinsic delay of the scaled inverter.


Japanese Journal of Applied Physics | 2006

Direct Measurement of Offset Spacer Effect on Carrier Profiles in Sub-50 nm p-Metal Oxide Semiconductor Field-Effect Transistors

Hidenobu Fukutome; Takashi Saiki; Ryou Nakamura; Akihiro Usujima; Takayuki Aoyama

We have directly measured the effect of the bottom shape in the offset spacer on the two-dimensional (2-D) carrier profiles of the sub-50 nm p-metal oxide semiconductor field-effect transistors (MOSFETs). It has been observed that the doping profile of the Sb pocket implanted with a high angle tilt is very sensitive to the bottom shape of the notched offset spacer. It has been confirmed that the Sb pocket deeply implanted leads to the decrease of 2 nm in the average overlap length of the extension region at a depth of 5 nm when the bottom shape is slightly upped at the notched offset spacer. The increased effective channel length is considered to enhance the dependence of the threshold voltage on the body bias voltage. Moreover, it is considered from the measured carrier profiles that the reduction in carrier concentration in the top channel region lowers the threshold voltage.


Japanese Journal of Applied Physics | 2005

Study of Gate Length Dependence of Two-dimensional Carrier Profile in N-FET by Scanning Tunneling Microscopy

Hidenobu Fukutome; Takayuki Aoyama; Hiroshi Arimoto

We measured the two-dimensional carrier profiles of n-type field effect transistors (n-FETs) with various gate lengths (Lg) by scanning tunneling microscopy. The extension overlap and the distribution of the depletion layers were evaluated to clarify that the measured carrier profiles were consistent with the roll-off characteristic of corresponding transistors. The effect of a pocket implant on a long transistor appeared where the lateral depletion width was locally shorter than the vertical one. In the n-FET with a gate length less than 40 nm, the effect of the pocket impurities from the opposite side mainly appeared as a reduction in the extension overlap in the deep region. Although the presence of this pocket increased the top channel concentration, the short length of the effective channel resulted in the spread of the depletion layer in the deep-channel region via the two-dimensional effect.


Archive | 2010

Impurity concentration measuring method, stm measuring method, and sts measuring method

Hidenobu Fukutome; Shigehiko Hasegawa; Hisao Nakajima; 尚男 中島; 秀暢 福留; 繁彦 長谷川

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