Mitsuaki Hori

Advanced channel engineering achieving aggressive reduction of V T variation for ultra-low-power applications

We have achieved aggressive reduction of V<inf>T</inf> variation and V<inf>DD-min</inf> by a sophisticated planar bulk MOSFET named ‘Deeply Depleted Channel ™ (DDC)’. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing. The 2x reduction of V<inf>T</inf> variation in 65nm-node has been demonstrated by matching SRAM pair transistors, 2x improvement in SRAM static noise margin (SNM) and 300 mV V<inf>DD-min</inf> reduction of 576Kb SRAM macros to 0.425 V using conventional 6T cell layout.

A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (VT) variation, lower supply voltage (VCC), enhanced body effect and IEFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower VDD, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.

Angle-resolved photoelectron spectroscopy on gate insulators.

Abstract This work reviews the study of the chemical composition and the chemical structure of ultrathin oxynitride films using angle-resolved photoelectron spectroscopy. The nearest and the second nearest neighbors of a nitrogen atom in oxynitride films were determined from the deconvolution of N 1s spectra. It was found by applying maximum entropy concept to the angle resolved Si 2p and N 1s photoelectron spectra that the distribution of nitrogen atoms and their bonding configurations in oxynitride films formed by the plasma nitridation is quite different from those in oxynitride films formed by the interface nitridation.

Characterization of Plasma Nitridation Impact on Lateral Extension Profile in 50 nm N-MOSFET by Scanning Tunneling Microscopy

The electrical performances of sub-50-nm n-metal-oxide-semiconductor field effect transistors (n-MOSFETs) are improved when a plasma nitridation process is used after the gate electrodes are formed. The maximum drive current is increased by 2% and the minimum gate length is shrunk by 5% while the off-leakage current is maintained. Inverse modeling suggested that these improvements were due to nitridation-induced changes in the two-dimensional carrier profile, and scanning tunneling microscopy confirmed that they were. The plasma nitridation decreased the overlapping length from 12 nm to 10 nm and increased the steepness of the lateral abruptness of the extension region from 3.6 nm/decade to 1.8 nm/decade. Such an optimized profile is thought to be mainly due to nitrogen suppressing the lateral anomalous diffusion of the arsenic piled-up along the interface between the silicon substrate and the insulating layer.

Embedded FLOTOX flash on ultra-low power 55nm logic DDC platform

We have successfully embedded flash memory on an ultra-low power (<;0.9V) 55nm Deeply Depleted Channel™ (DDC) platform. In spite of reduced thermal budget of DDC process, single-bit charge loss (SBCL) of flash after cycling can be optimized and is comparable to that of baseline embedded flash. We have also verified that improved variability and resultant ultra-low power digital performance of the DDC process is maintained in an embedded flash flow.

Characterization of millisecond-anneal-induced defects in SiON and SiON/Si interface by gate current fluctuation measurement

In this paper, we have investigated bulk trap and interface trap density (Dit) caused by millisecond annealing (MSA) using gate current fluctuation (GCF) and charge pumping measurements. We show that the high energy flash lamp annealing (FLA) creates the GCF with a long duration time and it is critical issue to get a stable SRAM operation. FLA creates interface traps localized at the gate edge of MOSFET.