Takashi Saiki

MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node

NMOSFET strain engineering using highly tensile silicon nitride capping layer was studied by way of extensive numerical simulations and device experiments. At 45nm gate length and 1V supply voltage fabricated NMOSFET delivers 1.00mA/ /spl mu/m drive current for off-state current of 40nA/ /spl mu/m and physical gate oxide thickness of 1.25nm(TEM). These data demonstrate the best up to date NMOSFET current drivability. Next, using extensive process simulations to analyze fabricated devices we developed optimization guidelines for NMOSFET strain engineering enabling us further improvement of device current drivability with reducing the gate length.

Performance Boost using a New Device Design Methodology Based on Characteristic Current for Low-Power CMOS

The authors proposes a characteristic current (I_chr) to replace the conventional saturation drive current used to estimate approximate CMOS inverter delay times for deeply scaled devices. The authors also present a new device design method based on I_chr to achieve a higher operation frequency for CMOS inverter circuits. The new method shortens propagation delay time (Tpd) by 15%

Characterization of Plasma Nitridation Impact on Lateral Extension Profile in 50 nm N-MOSFET by Scanning Tunneling Microscopy

The electrical performances of sub-50-nm n-metal-oxide-semiconductor field effect transistors (n-MOSFETs) are improved when a plasma nitridation process is used after the gate electrodes are formed. The maximum drive current is increased by 2% and the minimum gate length is shrunk by 5% while the off-leakage current is maintained. Inverse modeling suggested that these improvements were due to nitridation-induced changes in the two-dimensional carrier profile, and scanning tunneling microscopy confirmed that they were. The plasma nitridation decreased the overlapping length from 12 nm to 10 nm and increased the steepness of the lateral abruptness of the extension region from 3.6 nm/decade to 1.8 nm/decade. Such an optimized profile is thought to be mainly due to nitrogen suppressing the lateral anomalous diffusion of the arsenic piled-up along the interface between the silicon substrate and the insulating layer.

1st quantitative failure-rate calculation for the actual large-scale SRAM using ultra-thin gate-dielectric with measured probability of the gate-current fluctuation and simulated circuit failure-rate

We investigated the influence over intermittent SRAM failure by gate current, Ig, fluctuation for the first time. In this paper, we also describe the difference of SRAM failure due to Ig fluctuations between MOS transistors before and after stressing. We have quantitatively confirmed that Ig fluctuation causes SRAM failure.

Dependence of Sheet Resistance of CoSi2 with Gate Length of 30 nm on Thickness of Titanium Nitride Capping Layer in Co-Salicide Process

Since the distribution of gate resistance using cobalt silicide (CoSi2) increases markedly for gate lengths of 30 nm or less, CoSi2 is now being replaced by NiSi. However, CoSi2 still has the advantages of a high thermal stability and a low degree of roughness at the interface between the silicide and silicon layers owing to the low degree of mismatch (1.2%) of between their lattice constants. We have achieved excellent sheet resistance (Rs) with a gate length Lg=30 nm by optimizing the thickness of a cobalt capping layer of titanium nitride. The results shows an abnormal Rs behavior, in which one σ of Rs increases with capping layer thickness in the range of 10–50 nm, while it decreases with increasing capping layer thickness in the range of 0–10 nm. Unlike the results of a previous report [K. Goto et al.: IEDM Tech. Dig., 1995, p. 449], the variation in the Rs with a gate length Lg=30 nm is small, even without a TiN capping layer thickness down to 5–10 nm. We suggest that the uniformity of Rs is determined by the thickness of the CoSi layer after selective etching and the titanium concentration in the CoSi layer for capping TiN thicknesses of 10–50 nm, while the uniformity is determined by the titanium concentration and the damage sustained during selective etching for TiN thickness of 0–10 nm. For this optimization, CoSi2 is applicable to the 65 nm node technology node or beyond.

Dependence of CoSi2 Sheet Resistance on Cobalt Thickness for Gate Lengths of 50 nm or Less

In this paper, we report a novel process for reducing a large distribution of sheet resistance (Rs) of CoSi2 with a low resistivity of 18 µΩ cm [O. Akhavan et al.: Appl. Sur. Sci. 233 (2004) 123] in narrow lines by establishing a simple model for explaining the dependence of Rs on the gate length (Lg). We prove that the distribution of Rs is mainly influenced by the shape of the high resistivity (147 µΩ cm) cobalt monosilicide (CoSi) phase [A. Applebaum et al.: J. Appl. Phys. 57 (2005) 1880] formed in the first rapid thermal annealing (RTP-1) in the salicide process, and demonstrate that a tight distribution of Rs for Lg=30 nm can be achieved by optimizing the cobalt thickness to enhance the transformation to CoSi2.

Direct Measurement of Offset Spacer Effect on Carrier Profiles in Sub-50 nm p-Metal Oxide Semiconductor Field-Effect Transistors

We have directly measured the effect of the bottom shape in the offset spacer on the two-dimensional (2-D) carrier profiles of the sub-50 nm p-metal oxide semiconductor field-effect transistors (MOSFETs). It has been observed that the doping profile of the Sb pocket implanted with a high angle tilt is very sensitive to the bottom shape of the notched offset spacer. It has been confirmed that the Sb pocket deeply implanted leads to the decrease of 2 nm in the average overlap length of the extension region at a depth of 5 nm when the bottom shape is slightly upped at the notched offset spacer. The increased effective channel length is considered to enhance the dependence of the threshold voltage on the body bias voltage. Moreover, it is considered from the measured carrier profiles that the reduction in carrier concentration in the top channel region lowers the threshold voltage.