Hidenori Murata
Osaka University
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Publication
Featured researches published by Hidenori Murata.
electronic components and technology conference | 2011
Akihiro Tsukada; Ryohei Sato; Shigenobu Sekine; Ryuji Kimura; Keijiroh Kishi; Yukihiro Sato; Yoshiharu Iwata; Hidenori Murata
We focus on 3D-SiP using TSVs as one possible breakthrough method that can overcome semiconductor scaling limits. To this point, despite numerous investigations, this method has not reached mass production due to many problems in processing, structure, mass production, reliability, etc… In particular, typical filling methods used in the current TSV such as Cu electro-plating, W-CVD and the like have poor manufacturability and are limited to holes with small aspect ratios making practical adoption a problematic. To overcome this obstacle, we have developed a new Bi-Sn liquid metal filling method that is completely different from previous methods. In this method, we first form a high aspect ratio (>25) miniature via (about 1μm) using RIE dry etching on a Si wafer. Filling is performed by melting metal in a vacuum, and then applying pressure. For this purpose, we have developed a new Bi-Sn filler material that expands when it congeals, and can withstand temperatures >250C. Our landmark method makes it possible to increase the speed of filling a TSV by over 10 times, i.e., several minutes for a 12 inch wafer, as well as make it possible to fill a TSV with super high aspect ratio. In this work we provide an overview of the method and report on the characteristics of the new filler material. As a result Compared with the Cu-TSV, there is almost no Keep Out Zone using this material. It was clearly shown that this contributes to increased gate density.
ieee international d systems integration conference | 2012
Ryohei Sato; Akihiro Tsukada; Yukihiro Sato; Yoshiharu Iwata; Hidenori Murata; Shigenobu Sekine; Ryuji Kimura; Keijiroh Kishi
We focus on 3D-SiP using TSVs as one possible breakthrough method that can overcome semiconductor scaling limits. Despite numerous investigations, this method has not reached mass production due to many problems in processing, structure, mass production, reliability, etc... In particular, typical filling methods used in the current TSV such as Cu electro-plating, W-CVD and the like have poor manufacturability and are limited to holes with small aspect ratios making practical adoption problematic. To overcome this obstacle, we have developed a new Bi-Sn liquid metal filling method that is completely different from previous methods. In this method, we first form a high aspect ratio, miniature via using RIE dry etching on a Si wafer. Filling is performed by melting alloy in a vacuum, and removing the melted alloy residue with pressurization. For this purpose, we have developed a new Bi-Sn-Ag filler material that expands when solidifying, and can withstand temperatures >;250C. Our landmark method makes it possible to increase the speed of filling a TSV by several minutes for a 12 inch wafer, as well as make it possible to fill a TSV with super high aspect ratio(>;40), super fine via(about 0.2μm) and no Keep Out Zone (KOZ) using this material.
international conference on electronic packaging and imaps all asia conference | 2015
Ken Kawamura; Hidenori Murata; Yoshiharu Iwata; Ryohei Satoh; Takeshi Sakamoto; Kazuya Okamoto
An efficient design of a radiation measurement system using the SDSI-Cubic (System Design System Integration-Cubic) is demonstrated. The system itself is embedded requiring a smaller-form factor, higher cost performance amongst other things. In addition to sensor design, the implementation of various functionalities such as waveform processing and calculation is designed by proper assignment/implementation to hardware (analog circuits and FPGA) or software for the CPU. Moreover, the entire system accounting for multiple subsystem designs with conflicting requirements is optimized. By optimizing the system configuration, the first portable radiation dose and radioactivity measurement system is developed.
electronic components and technology conference | 2009
Atsushi Taya; Yoshiharu Iwata; Ryohei Satoh; Hidenori Murata; Eiji Morinaga; Keiji Kudo; Kazuya Okamoto
In this paper we construct a system design method for 3D integration. We report the use of this method to predict suitable 3D-SiP structures. 3D integration design is expected to be the breakthrough needed to overcome the apparent limits on design rule scaling in regimes where previous design methods have become difficult to implement. Given this current situation, we propose a method that assists in the design of large scale/complex systems that are representative of LSI systems. We use this method to predict suitable 3DSiP structures in the rough design phase.
Journal of Smart Processing | 2014
Hidenori Murata; Yoshiharu Iwata; Ryohei Satoh; Eiji Morinaga; Kazuya Okamoto; Kazuhiro Aoyama; Tsuyoshi Koga
Journal of Japan Institute of Electronics Packaging | 2014
Hidenori Murata; Yoshiharu Iwata; Atushi Taya; Ryohei Satoh; Eiji Morinaga; Kazuya Okamoto; Keiji Kudo; Kazuhiro Aoyama; Tsuyoshi Koga
Archive | 2010
Yoshiharu Iwata; Ryohei Satoh; Keiji Kudo; Atsushi Taya; Kazuya Okamoto; Hidenori Murata; Koichiro Atsumi; Eiji Arai; Eiji Morinaga
Procedia CIRP | 2018
Hidenori Murata; Hideki Kobayashi; Shinichi Fukushige
Journal of Japan Institute of Electronics Packaging | 2018
Ken Kawamura; Hidenori Murata; Takeshi Sakamoto; Ryohei Satoh; Yoshiharu Iwata; Eiji Arai; Kazuya Okamoto
The Proceedings of Manufacturing Systems Division Conference | 2017
Ken Kawamura; Hidenori Murata; Takeshi Sakamoto; Ryohei Satoh; Yoshiharu Iwata; Eiji Ara; Kazuya Okamoto