Yoshiharu Iwata

Study on TSV with new filling method and alloy for advanced 3D-SiP

We focus on 3D-SiP using TSVs as one possible breakthrough method that can overcome semiconductor scaling limits. To this point, despite numerous investigations, this method has not reached mass production due to many problems in processing, structure, mass production, reliability, etc… In particular, typical filling methods used in the current TSV such as Cu electro-plating, W-CVD and the like have poor manufacturability and are limited to holes with small aspect ratios making practical adoption a problematic. To overcome this obstacle, we have developed a new Bi-Sn liquid metal filling method that is completely different from previous methods. In this method, we first form a high aspect ratio (>25) miniature via (about 1μm) using RIE dry etching on a Si wafer. Filling is performed by melting metal in a vacuum, and then applying pressure. For this purpose, we have developed a new Bi-Sn filler material that expands when it congeals, and can withstand temperatures >250C. Our landmark method makes it possible to increase the speed of filling a TSV by over 10 times, i.e., several minutes for a 12 inch wafer, as well as make it possible to fill a TSV with super high aspect ratio. In this work we provide an overview of the method and report on the characteristics of the new filler material. As a result Compared with the Cu-TSV, there is almost no Keep Out Zone using this material. It was clearly shown that this contributes to increased gate density.

Development of Au reflection film with high adhesion for high-density optical interconnection between LSI chips

We have developed a new multilayered reflection film structure containing Au for achieving slab waveguide based optical transmission interconnections between large-scale integration chips for next-generation high speed computers. The noble metals, especially Au, have outstanding characteristic as a high reflection film in a slab waveguide. However, when these metals are combined with optically transparent films of a SiO/sub 2/ system, there are severe problems with poor adhesion and poor thermal stability. In this work, we have solved these problems by inserting Cr films above and below the Au film resulting in the development of a new multilayered reflection film structure with superior reflectivity and adhesion characteristics.

Study on high performance and productivity of TSV's with new filling method and alloy for advanced 3D-SiP

We focus on 3D-SiP using TSVs as one possible breakthrough method that can overcome semiconductor scaling limits. Despite numerous investigations, this method has not reached mass production due to many problems in processing, structure, mass production, reliability, etc... In particular, typical filling methods used in the current TSV such as Cu electro-plating, W-CVD and the like have poor manufacturability and are limited to holes with small aspect ratios making practical adoption problematic. To overcome this obstacle, we have developed a new Bi-Sn liquid metal filling method that is completely different from previous methods. In this method, we first form a high aspect ratio, miniature via using RIE dry etching on a Si wafer. Filling is performed by melting alloy in a vacuum, and removing the melted alloy residue with pressurization. For this purpose, we have developed a new Bi-Sn-Ag filler material that expands when solidifying, and can withstand temperatures >;250C. Our landmark method makes it possible to increase the speed of filling a TSV by several minutes for a 12 inch wafer, as well as make it possible to fill a TSV with super high aspect ratio(>;40), super fine via(about 0.2μm) and no Keep Out Zone (KOZ) using this material.

An Efficient Thermal Design Method Based on Boundary Condition Modeling

Until recently, layout design methods for electronic devices such as large scale integration circuits (LSIs) have been considered strictly from the viewpoint of electrical circuit design. In the near future, however, electronic system design will also require thermal design as well. Current thermal layout design is treated as power distribution in electrical layout design. But, evaluation of thermal design is not power density. That is a temperature of the chip. In the process, the designer faces problems. Evaluation of temperature needs the thermal analysis. And, the thermal analysis is slower than electrical evaluation. This, in turn, accentuates the need to accelerate thermal analysis and design methods. We have been investigating a novel high-speed thermal management method for the upper-stream of electronic device layout design on modules when the designer is interested in narrowing down possible design solutions. This method has four features, i.e., 1) division of elements on modules by the boundary conditions, 2) high-speed thermal analysis (10-mus order), 3) division of design by inter-module boundary conditions to three design layers, and 4) automatic identification of regions in design space that satisfy the design constraints. As an illustration, we performed a layout design of a board with four device modules mounted on top with 16 design parameters. Our method achieves the very fast design time (150 s) with 4*105 analysis

Cathodoluminescence Microcharacterization of Radiative Recombination Centers in Lifetime-Controlled Insulated Gate Bipolar Transistors

Cross-sectional cathodoluminescence (CL) measurements were applied to the study of electron-irradiated punch-through insulated gate bipolar transistors (IGBTs) to investigate the relationship between radiative recombination centers and electrical characteristics. IGBTs were additionally annealed at temperatures of 200–400 °C for 1 h. As annealing temperature rose, collector–emitter saturation voltage (VCES) decreased and current fall time (tf) increased. The cross-sectional CL measurements showed sharp luminescent peaks at 1018 meV (W or I1), 1040 meV (X or I3), and 790 meV (C) and a broad band at approximately 0.90–1.05 eV. As annealing temperature rose, the intensity of the W line decreased and that of the X line increased, suggesting that small self-interstitial clusters agglomerate and form stable, large self-interstitial clusters reducing the total number of self-interstitial clusters. The C line, which originated from an interstitial oxygen and carbon complex, showed no significant change. We consider that self-interstitial clusters play important roles in the electrical characteristics of lifetime-controlled IGBTs.

Study of extreme low temperature and load solid-phase Sn-Ag system bonding mechanism for 3D ICs

The objective of this study is i) to optimize a new nano solid phase, Ag-Sn thin-film bonding system for wafer-level 3D-stacking for 3D ICs, and ii) to clarify its bonding mechanism. As reported in our previous study, we achieved bonding at a much lower temperature (180°C), with lower load (0.4MPa) and much shorter time (5 min) compared to Cu-Cu direct bonding. Moreover, the bonded interface had high heat resistance (> 480°C) when we deposit the main bonding material of Sn (low melting point metal) and Ag (formation compound with Sn) as a multi-layer film. By performing detailed analysis using TEM, we find that formation of Sn-Ag type intermetallic compound occurs and that the bonding volume contracts, i.e., Sn+Ag ⇒ Sn-Ag IMC: about 6%. This contraction results in extremely high pressure being applied to an un-bonding process caused by micron roughness and an impurity layer, e.g., oxide, at the interface. A bonding process we call “self-compression bonding” then sequentially proceeds at unbonded interface regions. We hypothesize good bonding is achieved over the entire interface in a short time period due to self-compression bonding.

Study of low temperature and high heat-resistant fluxless bonding via nanoscale thin film control toward wafer-level multiple chip stacking for 3D LSI

The three dimensional system in package (3D-SiP) has been regarded as a promising solution to the scaling limit problem in the semiconductor industry. Practical realization of the 3D-SiP needs establishing a standard bonding technology for chip stacking. This research focuses on a low temperature and high heat-resistant fluxless bonding method, which can overcome the bump height variation problem in a chip/wafer, using high-boiling alcohol, an indium-tin (InSn) thin film and its transformation into high-melting intermetallic compound (IMC). Experimental studies showed high-rate deposition of InSn alloy and successive deposition of silver achieve successful bonding where the joint has high melting point (higher than 673K).

A Design Method for Thin Film Patterning Process via Lift-Off Technique

Thin film patterning by a lift-off method is effective from the viewpoint of cost performance and environmental issues. As a solution to the problems of conventional lift-off methods, the inversely-tapered resist profile with interstice was proposed and its fundamental feasibility was experimenatally proved. The resist profile still needed to be designed properly to solve the problems completely, and therefore a design method was also suggested. The method presupposes that conditions of deposition process have been already determined. However, actually, the conditions relate closely to the design of resist profile and wrong conditions may result in undesirable or infeasible design result. This paper proposes an integrated design method of the thin film patterning process considering design of both resist profile and deposition conditions.

P-210: Ta-Doped SnO2 Thin Films for PDP

SnO2 is considered to be a promising alternative material for indium tin oxide (ITO), which is used for transparent electrode in Flat Panel Display (FPD) and is facing a serious indium depletion problem. However, there are some problems such as high resistance, difficulty in processing, and low sintered density, which is necessary to sputtering. We investigated Ta-X doped SnO2. Doping these elements enabled sintered density to rise and its specific resistance to decrease below 1.0×10−2Ω⋅cm after dielectric firing, it is low enough to apply to plasma display panel (PDP). Furthermore, the films which we formed were easy to process by YAG laser. Therefore, it is favorable material for transparent electrode of PDP.

60.2: Research on Next‐Generation Manufacturing Method of Plasma Display Panels via Lift‐Off Process

This paper aims to develop the next-generation manufacturing method of plasma display panels (PDPs) which is superior in cost-performance and environmental damage to current methods, by introducing the lift-off process in place of the etching process. The lift-off process, which has been applied in the LSI fields, has been faced problems caused by inappropriate resist profiles, such as difficulty in resist removal and low pattern accuracy. Moreover, in PDP processes, inappropriate profiles cause more serious problems. In this paper, the inversely tapered and T-shaped resist profile is proposed, and its feasibility is experimentally proved. for proper design of the proposed profile, deposition model onto the profile is discussed, and a method based on the model is given.