Hideo Funakoshi

First photomask developer based on state-of-the-art wafer processing technology

The challenges, mask manufacturing is faced with, are more and more dominating the semiconductor industry as the pattern sizes shrink. Todays mask patterns have reached sizes that are common in wafer manufacturing. Looking into the industry, we can see that some of the quality parameters - such as CD uniformity and defect control - are managed better in wafer than in mask manufacturing. Consequently, mask manufacturers have started to apply more wafer processing techniques to mask processes. Among others, develop process has a great impact on the quality of the mask manufacturing. This contribution describes how Tokyo Electron Limited (TEL) scanning (linear drive nozzle) developer processing (widely used in advanced wafer manufacturing) was adapted for mask development. Out of this technology transfer, a new alpha-type mask develop tool was launched at TEL and an evaluation of this tool was carried out at the Advanced Mask Technology Center (AMTC), Dresden, Germany. Target of this collaboration was to successfully transfer wafer processing technology to mask making. By this, valuable information was generated, that has been implemented into the production platform, which is commercialized since first half of 2004.

New development system for EUV mask

EUV lithography is one of the approaches to manufacture half-pitch 1x nm devices. It is required high CD mean control, high CD uniformity, and low defect density for EUV mask in common with DUV mask. In addition, backside defect density is drastically tightened to avoid overlay error in EUV scanner. PGSD (Proximity-Gap-Suction-Development), a novel development system we developed, has kept upgrading to satisfy the demand of most-advanced devices, and 3rd-generation PGSD (PGSD Gen. III) which developed for EUV mask will be contributed to achieve required accuracy of EUV mask. In this paper, we propose the concept of PGSD Gen. III and report its performance.

Study of electric-field-induced-development method

Mask development process for 2x nm node devices needs stringent CD uniformity and CD linearity. To evaluate and improve these CD qualities, we proposed to introduce electric-field-induced-development method into proximity gap suction development system (PGSD). It is the way to develop with applying electric potential to the metallic development nozzle to stimulate the movement of hydroxide ions. In this paper, we will report the effect of electric-field-induced-development method on CD uniformity and CD linearity.

More evolved PGSD (proximity gap suction developer) for controlling movement of dissolution products

PGSD is one of the solutions as a developer of 70 nm node generation mask fabrication. To make 55 nm node generation mask, CD error induced by loading effect (loading-effect-induced CD error) must be reduced. As is generally known, primary cause of loading effect is dissolution products that hinder the progress of development. We think that it is the key in development technology to control movement of dissolution products and to disperse dissolution products uniformly for minimizing the loading-effect-induced CD error. In this paper, we propose a new concept and procedure to optimize the movement direction and the amount of dissolution products.

Application of PGSD (proximity gap suction development) to 70 nm NAND mask fabrication

CD error caused by loading effect is becoming a significant issue in mask fabrication. At the same time, quantification method of CD error caused by loading effect has not been established in many cases because it is very difficult to measure the error according to various coverages. In previous studies, we presented the development equipment named PGSD (Proximity Gap Suction Development). PGSD can reduce loading error of development process by using of nozzles to spout developer and suck in dirty developer. However, in the case of using PGSD for development process, CD error caused by loading effect seems to still remain. In this paper, we propose a new method to quantify the error caused by loading effect, and estimate the development-induced error out of total CD error. We evaluated 70 nm NAND mask by investigating the correlation between CD and coverage. Moreover, we discuss the residual CD error excluding the loading effect.