Naoya Hayashi

Phase controllability improvement for alternating phase shift mask

An alternating phase shift masks can improve resolution and lithographic latitude. However, Alt-PSMs have not yet become practical because of difficulty in their tight phase and defect control. In this paper, we focused on how to control both phase uniformity and phase mean value of etched quartz shifters. We found that a material of a dry-etching tale (cover plate of work electrode) was strongly affected for phase uniformity. By choosing an adequate material, phase uniformity of 1.9% could be achieved. Micro-loading effect and loading effect degrade phase controllability. Loading effect was not observed in our etching conditions. But micro-loading effect was observed. Back exposure process was useful to prevent micro-loading effect. To improve mean value controllability, 2 step etching process was adopted. By using this method, mean value cold be controlled within plus or minus 2 degrees.

LER transfer from a mask to wafers

Contribution of mask line edge roughness (LER) to resist LER on wafers was studied both by simulations and experiments. LER transfer function (LTF) introduced by Naulleau and Gallatin was generalized to include the effect of mask error enhancement factor (MEEF). Low spatial frequency part of LTF was enhanced by MEEF while high spatial frequency part was suppressed due to the numerical aperture limit of a stepper. Our model was experimentally verified as follows. First LER of a mask was measured by a scanning electron microscope. Then the mask LER was multiplied by LTF to simulate the aerial image LER on wafers. It was confirmed that the simulated LER agreed well with the LER measured by AIMSTM. Based on our model the contribution of the mask LER to the resist LER on wafers was estimated. According to our estimation the requirement of the mask LER should be as tight as that of the resist LER on wafers.

Performance of EBeyeM for EUV Mask Inspection

According to the ITRS Roadmap, the EUV mask requirement for 2X nm technology node is detection of defect size of 20 nm. The history of optical mask inspection tools involves continuous efforts to realize higher resolution and higher throughput. In terms of productivity, considering resolution, throughput and cost, we studied the capability of EUV light inspection and Electron Beam (EB) inspection, using Scanning Electron Microscope (SEM), including prolongation of the conventional optical inspection. As a result of our study, the solution we propose is EB inspection using Projection Electron Microscope (PEM) technique and an image acquisition technique to acquire inspection images with Time Delay Integration (TDI) sensor while the stage is continually moving. We have developed an EUV mask inspection tool, EBeyeM, whole design concept includes these techniques. EBeyeM for 2X nm technology node has the following targets, for inspection sensitivity, defects whose size is 20 nm must be detected and, for throughput, inspection time for particle and pattern inspection mode must be less than 2 hours and 13 hours in 100 mm square, respectively. Performance of the proto-type EBeyeM was reported. EBeyeM for 2X nm technology node was remodeled in light of the correlation between Signal to Noise Ratio (SNR) and defect sensitivity for the proto-type EBeyeM. The principal remodeling points were increase of the number of incident electrons to TDI sensor by increasing beam current for illuminating optics and realization of smaller pixel size for imaging optics. This report presents the performance of the remodeled EBeyeM (=EBeyeM for 2X nm) and compares it with that of the proto-type EBeyeM. Performances of image quality, inspection sensitivity and throughput reveal that the EBeyeM for 2X nm is improved. The current performance of the EBeyeM for 2X nm is inspection sensitivity of 20 nm order for both pattern and particle inspection mode, and throughput is 2 hours in 100 mm square for particle inspection mode.

EUVL practical mask structure with light shield area for 32nm half pitch and beyond

The effect of mask structure with light shield area on the printability in EUV lithography was studied. When very thin absorber on EUVL mask is used for ULSI application, it then becomes necessary to create EUV light shield area on the mask in order to suppress possible leakage of EUV light from neighboring exposure shots. We proposed and fabricated two types of masks with very thin absorber and light shield area structure. For both types of masks we demonstrated high shield performances at light shield areas by employing a Small Field Exposure Tool (SFET).

Process development for EUV mask production

Absorber layer patterning process for low reflectivity tantalum boron nitride (LR-TaBN) absorber layer and chromium nitride (CrN) buffer layer were improved to satisfy high resolution pattern and high level critical dimension (CD) control. To make 100nm and smaller pattern size, under 300nm resist thickness was needed because of resist pattern collapse issue. We developed absorber layer dry etching process for 300nm thickness resist. Absorber layer patterning was done by a consequence of carbon fluoride gas process and chlorine gas process. We evaluated both gas processes and made clear each dry etching character. Sufficient resist selectivity, vertical side wall, good CD control and low buffer layer damage were obtained. Then, we evaluated how buffer layer dry etching affects EUV reflectivity. Finally, we evaluated EUV mask pattern defect inspection and defect repair. Sufficient contrast of mask pattern image and good repair result were obtained using DUV inspection tool and AFM nano-machining tool, respectively.

Vortex via process: analysis and mask fabrication for contact CDs <80 nm

In an optical vortex, the wavefront spirals like a corkscrew, rather than forming planes or spheres. Since any nonzero optical amplitude must have a well-defined phase, the axis of a vortex is always dark. Printed in negative resist at 248nm and NA=0.63, 250nm pitch vortex arrays would produce contact holes with 80nmk1<0.4), depending on exposure dose. Arrays of vortices with kpitch>0.6 can be patterned using a chromeless phase-edge mask composed of rectangles with nominal phases of 0°, 90°, 180° and 270°. Analytic and numerical calculations have been performed to characterize the aerial images projected from such vortex masks using the Kirchhoff-approximation and rigorous EMF methods. Combined with resist simulations, these analyses predict process windows with ≈10%Elat and >200nm DOF for 80nm CDs on pitches greater than or equal to 250nm at σ greater than or equal to 0.15. Smaller CDs and pitches are possible with shorter wavelength and larger NA while larger pitches give rise to larger CDs. At pitch >0.8μm, the vortices begin to print independently for σ greater than or equal to 0.3. Such “independent” vortices have a quasi-isofocal dose that gives rise to 100nm contacts with Elat>9% and DOF>500nm at σ=0.3. The extra darkness of the nominal 270° phase step can be accommodated by fine-tuning the etch depth. A reticle fabrication process that achieves the required alignment and vertical wall profiles has been exercised and test masks analyzed. In an actual chip design, unwanted vortices and phase step images would be erased from the resist pattern by exposing the wafer with a second, more conventional trim mask. Vortex via placement is consistent with the coarse-gridded grating design paradigms which would - if widely exercised - lower the cost of the required reticles. Compared to other ways of producing deep sub-wavelength contacts, the vortex via process requires fewer masks and reduces the overlay and process control challenges. A high resolution negative-working resist process is essential, however.

Study of EUV mask defect repair using FIB method

We evaluated a new FIB-GAE (Focused Ion Beam-Gas Assisted Etching) repairing process for the absorber defects on EUVL mask. XeF2 gas and H2O gas were used as etching assist agent and etching stop agent respectively. The H2O gas was used to oxidize Ta-nitride side-wall and to inactivate the remaining XeF2 gas after the completion of defect repair. At the Photomask Japan 2008 we had reported that side-etching of Ta-nitride caused CD degradation in EUVL. In the present paper we report on the performance of defect repair by FIB, and of printability using SFET (Small Field Exposure Tool). The samples evaluated, were in form of bridge defects in hp225nm L/S pattern. The cross sectional SEM images certified that the newly developed H2O gas process prevented side-etching damage to TaBN layer and made the side-wall close to vertical. The printability also showed excellent results. There were no significant CD changes in the defocus characterization of the defect repaired region. In its defect repair process, the FIB method showed no signs of scan damage on Cr buffered EUV mask. The repair accuracy and the application to narrow pitched pattern are also discussed.

Primary evaluation of proximity and resist heating effects observed in high-acceleration voltage e-beam writing for 180-nm-and-beyond rule reticle fabrication

Higher resolution and accuracy are required in e-beam lithography for reticle fabrication for coping with further advances in optical lithography. The trend is to use high acceleration voltage (50 kV) e-beam to improve spatial resolution. However, in the case of high acceleration e-beam writing, a drastic critical dimension (CD) change is caused by a strong proximity effect and a large resist heating effect. The proximity effect is caused by the increase in the back- scattering radius. The back-scattering radius was estimated by two independent observations of the CD variation of a monitor and the thickness variation of a partially developed resist. It is found to be ca. 15 nm. Using the shot time modulation as a proximity correction reduced the proximity effect to a small level: CD error due to the pattern density change remained within 10 nm. On the other hand, the resist heating effect is caused by the change in resist dissolution speed by the temperature rise of the resist. In reducing this effect, multi-pass writing is found to be effective. The range of the CD error of 2 micrometer lines-and-spaces in the writing field has been reduced from 22 nm to 6 nm by changing the writing from one pass to four passes for a conventional resist. Moreover, when a chemically amplified resist (CAR) is exposed through one-pass writing, the range of the CD error is found to be 8 nm. Therefore, the use of the CAR is effective in reducing the resist heating effect. Simulation software ProBEAM/3D and TEMPTATION were used to obtain three- dimensional resist profile and the transient temperature rise of the resist, respectively. Both provided results that agreed well with those by experiment.

Decomposition difficulty analysis for double patterning and the impact on photomask manufacturability

Double patterning technology (DPT) is one of the most practical candidate technologies for 45nm half-pitch or beyond while conventional single exposure (SE) is still dominant with hyper NA avoiding DPT difficulties such as split-conflict or overlay issue. However small target dimension with hyper NA and strong illumination causes OPC difficulty and small latitude of lithography and photomask fabricated with much tight specification are required for SE. Then there must be double patterning (DP) approach even for SE available resolution. In this paper DP for SE available resolution is evaluated on lithography performance, pattern decomposition, photomask fabrication and inspection load. DP includes pattern pitch doubled of SE, then lithography condition such as mask error enhancement factor (MEEF) is less impacted and the lower MEEF means less tight specification for photomask fabrication. By using Synopsys DPT software, there are no software-induced conflicts and stitching is treated to be less impact. And also this software detects split-conflicts such as triangle or square placement from contact spacing. For estimating photomask inspection load, programmed defect pattern and circuit pattern on binary mask are prepared. Smaller MEEF leads less impact to defect printing which is confirmed with AIMS evaluation. As an inspection result, there are few differences of defect sensitivity for only dense features and also few differences of false defect counts between SE and DP with less NA. But if higher NA used, DPs inspection sensitivity is able to be lowered Then inspection load for DP would be lighter than SE.

Development of nanoimprint lithography templates toward high-volume manufacturing

Abstract. Development of nanoimprint lithography (NIL) templates is discussed. The template fabrication process and its performance are presented with consideration of the requirements of NIL for high-volume manufacturing. Defectivity, image placement, and critical dimension uniformity are the three major performance parameters of the templates, and their current status is shown.