Masatoshi Kameyama

A DSP architectural design for low bit-rate motion video codec

A new digital signal processor (DSP) architecture is presented. This DSP consists of the usual components, such as instruction set, buses, data memories, execution unit, address generators, sequencer, and direct memory access controller, optimized for video signal processing. A 24-bit 50-ns DSP called the digital image signal processor (DISP) has been developed using 1- mu m CMOS technology. The performance of the DSP is evaluated by a benchmark test based on an actual video coding sequence. A multi-DSP configuration for a video codec that allows flexible algorithms and variable picture formats is studied. A low-bit-rate motion video codec can be built very easily using the DSPs presented by the authors. >

A DSP architecture for 64 kbps motion video codec

The authors describe an architectural study of a digital signal processor (DSP) well suited for video codec. This DSP consists of specified resources optimized for video signal processing, such as the instruction set, buses, data memories, execution unit, address generators, sequencer, and DMAC. The performance of the DSP is evaluated through several video coding sequences. The architecture of a multiprocessor configuration for video codec, which will allow flexible algorithm and variable picture format, is also examined.<<ETX>>