Hidetoshi Koike

A 1/2.5 inch 5.2Mpixel, 96dB Dynamic Range CMOS Image Sensor with Fixed Pattern Noise Free, Double Exposure Time Read-Out Operation

A 1/2.5 inch, 5.2 Mpeixel CMOS image sensor with wide dynamic range operation mode is developed and its effectiveness for high contrast scene pictures is verified. The adopted algorithm for this operation is inherently free from fixed pattern noise generation which often resists the realization of mass production level wide dynamic range image sensors. The attained dynamic range is 96 dB with 12 bit output scheme.

High performance copper and low-k interconnect technology fully compatible to 90nm-node SOC application (CMOS4)

Dual damascene copper and low-k (k=2.9) interconnect technology for 90nm-node was successfully integrated. Structure and process are optimized to be compatible to transistor, memories, and packaging with consideration of RC delay and crosstalk between lines. Especially, aspect ratio of metal1 was carefully studied with electromigration durability data and DRAM pause time distribution data, because bit lines of embedded DRAM were formed with metal1. In order to demonstrate feasibility for manufacturing, six copper metal layers were fabricated on transistors and memories.

Trench isolation technology with 1 /spl mu/m depth n- and p-wells for a full-CMOS SRAM cell with a 0.4 /spl mu/m n/sup +p/sup +/ spacing

This paper shows that 0.7 /spl mu/m depth shallow trench isolation with SiO/sub 2/ filling can achieve 0.4 /spl mu/m n+/p+ spacing, utilizing shallow p- and n-wells formation with retrograde profiles. An 80 degree taper trench with rounded edge accompanied by HCl ambient oxidation improves subthreshold characteristics and junction leakage. A 7.65 /spl mu/m/sup 2/ full-CMOS cell competitive to TFT cell size at 0.35 /spl mu/m design rule has been realized and a 256k bit SRAM has been fabricated.<<ETX>>

Dual-polycide gate technology using regrowth amorphous-Si to suppress lateral dopant diffusion

Process techniques for dual-polycide gate CMOS have been developed. The origin of lateral dopant diffusion is analyzed, and an enlarged-grain dual-polycide gate technology using regrowth amorphous-Si (a-Si) is proposed. Reduction of the dopant absorption into the silicide layer has been observed in the regrowth of a-Si polycide gate structure. Lateral dopant diffusion has been suppressed to less than 0.1 /spl mu/m, and, as a result, 0.2 /spl mu/m n-MOS/p-MOS spacing has been realized under an 850/spl deg/C furnace annealing process. This technology can also achieve current drivability improvement by suppressing the gate depletion simultaneously. Suppression of boron penetration through the gate oxide to the channel region from the p/sup +/ gate has been realized by gate doping ion implantation into the a-Si, and no threshold voltage lowering with small standard deviation has been confirmed. It has been recognized that the above techniques are a possible solution for the dual-polycide gate CMOS structure.

A 7000-gate microprocessor on SOS&#8212;PULCE

An n-channel MOS LSI microprocessor integrating 20 000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account. It is verified that a) the observed yield of a very large SOS chip is higher than the value predicted from a randomly distributed defects model, and b) the yield-sensitive active area of an SOS is so small that it can compensate for the yield degradation due to the very large defects density on an SOS wafer.

Simple and quick turnaround time fabrication process for deep submicrometer CMOS generation

Process simplification and turnaround time reduction for deep submicrometer CMOS fabrication are discussed. Process step analysis is carried out for standard 1Poly/1Metal CMOS structure, and consequently, both isolation and gate formation processes are extracted as items for process simplification. A combination of shallow trench isolation with retrograde well structure and single mask step well/gate doping technique is proposed for deep submicrometer CMOS fabrication. This simplified CMOS process can achieve a reduction of five mask steps and eliminates both well drive-in annealing and field oxidation without performance deterioration. As a result, a 10% process step reduction and a 20% manufacturing turnaround time reduction have been realized in comparison to the standard 1Poly/1Metal CMOS process with LOCOS isolation.

Process simplification in deep submicron CMOS fabrication

Process simplification in deep submicron CMOS fabrication is discussed. Process step analysis is carried out for standard 1Poly/1Metal CMOS structure, and consequently, both isolation and gate formation process are extracted as items to simplify the process. A combination of shallow trench isolation and single mask step well/gate doping is proposed for deep submicron CMOS fabrication. This new process can achieve a reduction of 5 mask steps and eliminates both well drive-in annealing and field oxidation without performance deterioration. As a result, 10% process step reduction and 20% manufacturing turn-around-time reduction have been realized in comparison to the standard 1Poly/1Metal CMOS process with LOCOS isolation.

Quick-turnaround-time improvement for product development and transfer to mass production

We describe equipment and facility operational methods in a production fab which are designed to achieve quick-turnaround-time (QTAT) manufacturing and ease product transfer from development to mass production. An advanced CIM system with precise lot management is introduced to keep the optimum balance of manufacturing TAT and throughput. Substantial end-user computing reduces the engineering holding time for handling development lots. In situ monitoring technologies are applied for the utilization enhancement of plasma-assisted equipment. A 9% manufacturing TAT reduction and a 14% throughput increase are estimated using a manufacturing simulator. The number of wafers in QTAT lots is reduced for processing time reduction. As a result, manufacturing TAT of QTAT lots with reduction from 24 wafers to three is reduced to 56% compared with that of normal lots in the production fab. This new production fab realizes QTAT development and agile product transfer from development to mass production with full process compatibility.

Guest Editorial Special Section on the 2012 International Symposium on Semiconductor Manufacturing

This special section presents extended versions of ten papers that were selected from papers presented at the 2012 International Symposium on Semiconductor Manufacturing.

Counter-Doped Surface Channel Metal-Oxide-Semiconductor Field-Effect Transistor with High Current Drivability and Steep Subthreshold Slope

A metal-oxide-semiconductor field-effect transistor (MOSFET) with a novel channel structure called a counter-doped surface channel (CDSC) is proposed. A unique characteristic of the CDSC MOSFET is that the channel current still exists at the surface, even though the counter-doped layer is formed. Experimental results confirm that the CDSC pMOSFET using an n+ poly-Si gate has the highest current drivability and the steepest subthreshold slope while maintaining a good short-channel-effect immunity compared with the surface channel (SC) and buried channel (BC) pMOSFET. The delay time with the CDSC pMOSFET represents 1.34-fold improvement in comparison to that with the SC pMOSFET.