Fumitomo Matsuoka

Stress controlled shallow trench isolation technology to suppress the novel anti-isotropic impurity diffusion for 45nm-node high-performance CMOSFETs

The most suitable STI filling process has been developed for 45nm-node SoC platform. We found that the stress induced anti-isotropic impurity diffusion, which causes the Vth lowering. This novel phenomenon has been controlled by optimizing the SOD/HDP-CVD hybrid STI filling structure. At the same time, 20% drive current improvements of nFET and pFET have been obtained.

Future perspective and scaling down roadmap for RF CMOS

Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100 nm gate length generations.

Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V/sub dd/ is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V/sub dd/s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V/sub dd/ and V/sub th/ are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V/sub dd/ should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V/sub dd/ for SRAM operation. In high-density SRAM, low V/sub th/ causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V/sub th/ should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V/sub dd/ for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.

Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET's

The analysis indicates that a thinner gate oxide nMOSFET shows smaller degradation. Mechanisms for the smaller degradation were analyzed using a simple degraded MOSFET model. It was found that the number of the generated interface states is defined uniquely by the amount of peak substrate current, independently from the gate-oxide thickness. The major cause of the smaller degradation in the thinner gate-oxide device is smaller mobility degradation due to the generated interface states. The degraded mobility was measured and formulated. The smaller mobility degradation is explained by the difference between the vertical electric field dependence of the Coulomb scattering term and that of the phonon term under the inversion condition. The effect of a larger channel conductance, due to the larger inversion charges for the thinner gate-oxide device, is the secondary cause for the smaller degradation. >

Low-resistivity poly-metal gate electrode durable for high-temperature processing

A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100 nm)WN/sub x/(5 nm)/poly-Si structure. The W/WSiN/poly-Si structure was found to be thermally stable even after annealing at 800/spl deg/C. The sheet resistivity of the W(100 nm)/WN/sub x/(5 nm)/poly-Si(100 nm) structure is as low as 1.5 /spl Omega//spl par//spl square/ and independent of line-width from 0.52 /spl mu/m to 0.12 /spl mu/m. The sheet resistivity of this layer structure is 40% lower than that of the W(100 nm)/TiN(5 nm)/poly-Si structure. In addition, an equivalent circuit simulation showed that the measured contact resistivity of W and poly-Si in the W/WSiN/poly-Si system did not affect the gate RC delay time. Finally, a process integration of the poly-metal gate electrode is discussed. A SiN capped poly-metal structure was demonstrated.

Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique

Gate density is ultimately increased to 2100 kGates/mm2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of -2.8% to +3.6% and Idsat change of -10% to +14% are removed from uncertain margin in 45 nm corner libraries.

A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs

This paper demonstrates a 100 nm generation SOC technology (CMOS IV) for the first time. Three types of core devices are presented with optimized gate oxynitrides for their stand-by power conditions. This advanced logic process is compatible with 0.18 /spl mu/m/sup 2/ trench capacitor DRAM and 1.25 /spl mu/m/sup 2/ 6 transistor SRAM. Two kinds of high V/sub dd/ devices can be prepared by the triple gate oxide process. Moreover, for mixed signal applications, Ta/sub 2/O/sub 5/ MIM capacitors are introduced into Cu and low-k interconnects.

Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique

Layout dependences for stress-enhanced MOSFETs including contact positioning, the second neighboring poly effect, and bent diffusion are modeled in 45-nm CMOS logic technology. It is found that the sensitivity of contact position in the channel direction is larger for PMOS with a higher stress liner than for NMOS. The effect of contact positions is modeled by using the distance of contact to gate (x) and the number of contacts (N). In terms of the gate-space effect, it is concluded that, in addition to the neighboring gates, second neighboring gates affect the channel stress. The effect of bent-shape diffusion is analyzed for NMOS and PMOS. For NMOS, the channel profile is affected by the bent shape. This can be described by the change of V th. For PMOS, the channel stress is modulated by the bent diffusion. The stress effect in bent-shape diffusion for PMOS is modeled with three geometrical parameters. The compact model is applied to the characterization of actual 45-nm cell libraries. It is confirmed that, with the constructed models and design flow, a saturation current (I dsat) change of -12%-14% is removed from the uncertain margin in 45-nm corner libraries.

High performance bulk planar 20nm CMOS technology for low power mobile applications

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.

A 65nm low power CMOS platform with 0.495/spl mu/m/sup 2/ SRAM for digital processing and mobile applications

In this paper, a 65nm CMOS platform featuring low power transistors and high density SRAM (CMOS5L) is reported. It offers wide range of Vth lineup and very low gate leakage as 0.06A/cm/sup 2/ by optimization of halo implantation and gate oxidation process. Pulse nitridation is applied to suppress Vth variations. Obtained characteristics of MOSFET places top class among devices reported. High density SRAM for CMOS5L with the cell size of 0.495/spl mu/m/sup 2/ is developed. We demonstrate highly stable operation by 7Mb CMOS5L SRAM array. This SRAM has low power property less than 100/spl mu/W.