Hideaki Harakawa

A 1/2.5 inch 5.2Mpixel, 96dB Dynamic Range CMOS Image Sensor with Fixed Pattern Noise Free, Double Exposure Time Read-Out Operation

A 1/2.5 inch, 5.2 Mpeixel CMOS image sensor with wide dynamic range operation mode is developed and its effectiveness for high contrast scene pictures is verified. The adopted algorithm for this operation is inherently free from fixed pattern noise generation which often resists the realization of mass production level wide dynamic range image sensors. The attained dynamic range is 96 dB with 12 bit output scheme.

Patterning strategy and performance of 1.3NA tool for 32nm node lithography

We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.

New embedded DRAM technology using self-aligned salicide block (SSB) process for 0.18 /spl mu/m SOC (system on a chip)

New embedded DRAM technology for 0.18 /spl mu/m SOC (system on a chip) using the self-aligned salicide block (SSB) process is proposed. This process technology provides full process compatibility with high performance logic and minimum number of process steps, resulting in low process cost and short TAT (turnaround time). We fabricated a DRAM array macro using this technology with Co salicide, dual work function gate and aluminum bitline processes, and confirmed excellent DRAM retention characteristics by using a negative wordline bias scheme.

Boron diffusion layer formation using Ge cryogenic implantation with low-temperature microwave annealing

It is shown that a low-sheet-resistance p-type diffusion layer with a small diffusion depth can be fabricated efficiently by cryogenic boron and germanium implantation combined with low-temperature (400 °C) microwave annealing. Compared with the conventional annealing at 1000 °C, a much smaller diffusion depth is obtained at the same sheet resistance. The low sheet resistance at 400 °C is due to microwave absorption in the surface amorphous layer, which is formed by cryogenic germanium implantation. However, the pn junction leakage was worse than that in conventional annealing, because crystal defects remain near the amorphous/crystal interface after microwave annealing. It is found that the pn junction leakage is improved greatly by cryogenic germanium implantation. These results show that a suitable combination of cryogenic implantation and microwave annealing is very promising for p-type diffusion layer technology.

Patterning performance of hyper NA immersion lithography for 32nm node logic process

We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.

Feasibility of Ultra-Low k1 Lithography for 28nm CMOS Node

We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the 28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask topography effect and the oblique-incidence. Using the rigorous lithography simulation considering the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum pitch required in 28nm node. The optimum mask plate and illumination conditions have been decided by simulation. The experimental results for 28nm node show that the minimum pitch patterns and minimum SRAM cell are clearly resolved by single exposure.

Chemical dry cleaning technology for reliable 65 nm CMOS contact to NiSi/sub x/

Nickel silicide (NiSi/sub x/) is being considered as a replacement for the currently used silicides. A native oxide film on the nickel silicide surface causes high contact resistance. The cleaning technology for removal of the oxide film on NiSi/sub x/ is a critical issue for 65 nm generation CMOS devices. The effect of a chemical dry treatment prior to contact metallization was studied. It was confirmed that the chemical dry treatment is effective for obtaining low stable contact resistance, and is a key technology for the high yield manufacture of CMOS devices.

ArF lithography technologies for 65 nm-node CMOS (CMOS5) with 30 nm logic gate and high density embedded memories

In this paper ArF lithography technology for 65nm-node CMOS with 30nm logic gate and high density embedded memories have been demonstrated. ArF step-and-scan exposure systems with 0.75NA are available under accurate lithography design with level specific focus and does error budgets. Also,the process steps with two kinds of lithography are implemented to fabricate GC pattern.