Hiromasa Takahashi

A 51.2 GOPS 1.0 GB/s-DMA single-chip multi-processor integrating quadruple 8-way VLIW processors

A 51.2-GOPS chip multi-processor integrates four 8-way VLIW embedded processors with 1.0 GB/s local-bus direct memory access. This IC completes MPEG2 MP@HL video-stream decoding at 68% of its processor capability without dedicated hardware. The 11.9 mm /spl times/ 10.3 mm chip is fabricated in a 90 nm 9M CMOS process and consumes 5 W at 533 MHz.

A 240K transistor CMOS array with flexible allocation of memory and channels

A CMOS masterslice will be reported, covering the design of basic cells to accommodate both logic unit and memory cells, wiring channels allocated in discrete units and logic and memory blocks placed in arbitrary positions of a cell array. Implementation of a 16×16b parallel multiplier with 16b×64w SRAM and 16b×256w ROM will be compared.A CMOS masterslice containing about 240K transistors is described. A new basic cell was designed for efficient construction of both logic and memory cells. For flexible allocation of wiring channels, logic unit cells, and memory blocks, about 30000 basic cells with no dedicated channel regions are spread throughout the chip, except in the I/O region. Logic and memory blocks can be placed anywhere on the chip. A test chip, developed to investigate the feasibility of the masterslice design, reveals densities of 230 gates/mm/SUP 2/, 230 bit/mm/SUP 2/, and 1900 bit/mm/SUP 2/ for a 16/spl times/16-bit multiplier, a 1K SRAM, and a 4K ROM, respectively.

A vector coprocessor architecture for embedded systems

We developed a DSP for wireless base-band processing on handheld devices. The DSP is composed of a scalar CPU and a vector unit. The architecture of the vector unit inherits that of vector processors for super computers, and we customized it for embedded systems. We evaluated the processor using several programs. The evaluation showed that our DSP performs 40 times faster than scalar CPU. The peak performance is 12GOPS@250MHz.

A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations

A full 64-bit floating-point processing unit (FPU) with a long horizontal instruction code for parallel operations without pipeline interlock is described. The FPU is implemented on a 1.0- mu m CMOS chip containing 300 K transistors and operating at 25 MHz. It runs at a peak rate of 50 MFLOPs and a sustained rate of 15.4 MFLOPs. The register-to-register latency of double and single-precision addition, subtraction and multiplication are 120 ns each. The latency of double-precision division is 640 ns and that of square root is 880 ns.<<ETX>>

A 1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

A microprocessor with single instruction multiple data stream (SIMD) architecture and as many as 170 media instructions for multimedia embedded systems meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and 3DCG image processing capabilities, (b) programming flexibility, and (c) low power dissipation and low cost. It also works as a general purpose microprocessor with mid-range performance. The microprocessor uses 0.21 /spl mu/m CMOS technology, and the chip achieves 2.16 GOPS/720 MFLOPS at a 180 MHz operation with 1.2 W dissipation.

A 64-bit floating point processing unit for a RISC microprocessor

Describes architecture, layout, and simulation methodology of a high performance 64-bit floating point processing unit (FPU) which is applicable to a RISC microprocessor. The FPU contains a floating point execution unit and a floating point controller for the SPARC S-25 microprocessor. The FPU supports SPARC floating point instructions based on the IEEE Standard for Binary Floating Point Arithmetic (ANSI/IEEE std. 754-1985). Operating frequency is 25 MHz and peak floating point computing performance is 12.5 MFLOPS when it is used with the S-25 SPARC microprocessor. The chip was designed using 0.8 mu m CMOS standard cell technology. The chip size is 16.4*16.4 mm and packaged into 179-pin PGA. Total transistor count was approximately 330000.<<ETX>>

A sub-micron CMOS echo canceller using a DSP cell

This report will cover a 45K gate chip designed using a silicon compiler. A 11.5×11.8mm die contains a DSP that was available as a pre-designed cell.

An 8-way VLIW embedded multimedia processor built in 7-layer metal 0.11/spl mu/m CMOS technology

A 533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8-way VLIW embedded multimedia processor occupies a 7.8/spl times/7.8 mm/sup 2/ die in a 7-layer metal 0.11 /spl mu/m CMOS at 1.2 V. VLIW, SIMD, dynamic branch prediction, non-aligned dual load/store mechanism and a crosstalk-aware design flow contribute to performance.