Hideyuki Kabuo

Accurate rounding scheme for the Newton-Raphson method using redundant binary representation

Proposes a new algorithm of estimation and compensation of the error effect for rounding in the case of implementation of division and square root using the Newton-Raphson method. The authors analyze the error of the hardware system to confirm the condition of the implementation with respect to this algorithm. Next, they describe in detail how to compensate the error by using this algorithm. Finally, they show that the hardware components for this algorithm, the direct rounding mechanism in the recode circuit and the sticky digit generating circuit, can be realized simply by improving the redundant binary representation multiplier. The number of increasing cycles for this new algorithm is only one, and the rounding result using this algorithm satisfies IEEE Standard 754 rounding perfectly. >

An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

This paper describes a 16-b fixed point digital signal processor (DSP), especially its multiply-accumulate (MAC) unit, memories, and instruction set. By adopting a redundant binary multiplier and a variable pipeline structure, this DSPs MAC unit, compared to a conventional MAC unit, consumes about 15% less power and operates 24% faster. Furthermore, its double-speed MAC mechanism can realize twice the performance of a single MAC operation while consuming only 69% more power. By being able to more finely control which portions of memory are activated, the data ROM and data RAMs precharge current was reduced to about 1/8 of the conventional ROM and RAMs. We redesigned the instruction set and reduced its width from 32 b to 24 b based on the analysis of data generated by simulating an application program on our previous DSP. The reduction in instruction width made our on-chip instruction memory size 33% smaller than the previous one. This chip is fabricated with a 0.5-/spl mu/m double-metal-layer CMOS process and achieves 80-MOPS-peak double speed multiply-accumulate performance.

Introduction to the Special Issue on the 2013 Symposium on VLSI Circuits

The 23 papers in this special issue were originally presented at the 2013 Symposium on VLSI Circuits, held in Kyoto, Japan, on June 12-14, 2013.

Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits

This issue of the IEEE JOURNAL OF SOLID-STATE CIRCUITS highlights some of the best papers from the 2012 Symposium on VLSI Circuits, which was held at the Hilton Hawaiian Village, Honolulu, Hawaii, USA, June 13-15, 2012. In 2012, the Symposium held its 26th meeting on state-of-the-art topics important to VLSI circuit and system designers, as well as device and process technology experts. Industry and academia from all over the world presented papers at the Symposium highlighting important technical contributions and recent advances in VLSI circuit design. The Symposium on VLSI Circuits received 386 submissions from 22 countries of which 97 papers were selected for presentation, covering a range of topics on digital, memory, analog, wireless and wireline communication circuits. From these presentations, the committee has selected 19 outstanding papers as highlights of the 2012 Symposium for publication in this issue of the Journal. They are presented with greater detail than in the Symposium digest. These papers were subject to the standard Journal review and rigorous referee process. We enjoyed working with the authors on these papers, and we certainly hope that the technical details presented in these papers will be valuable and enjoyable to the Journal reader.