Hideyuki Nakamizo

Concurrent Multiband Digital Outphasing Transmitter Architecture Using Multidimensional Power Coding

All-digital outphasing transmitter architecture using multidimensional power coding (MDPC) is proposed for noncontiguous concurrent multiband transmission with a high power efficiency. MDPC transforms multiband digital baseband signals into multibit low-resolution digital signals that drive switching-mode PAs. A prototype digital outphasing transmitter consists of two 1-GHz bandwidth GaN Class-D PAs and a Chireix power combiner. The two GaN PAs are driven by bipolar radio frequency (RF) pulse-width modulation (PWM) signals, which are transformed from a concurrent dual-band LTE signal by MDPC. The dual-band LTE signal with 15-MHz aggregate channel bandwidth at 240 and 500 MHz frequency band is transmitted with -30 and -37 dBc out-of-band emissions, respectively. Digital outphasing achieves more than two times higher coding efficiency than conventional concurrent dual-band digital transmitters with the same PAs in Class-S operation. Measured power coding efficiencies of 35.4% and 47.1% are observed with outphasing bipolar and 3-level RF PWM signals respectively, which are encoded from the dual-band LTE signal.

Over 65% PAE GaN voltage-mode class d power amplifier for 465 MHz operation using bootstrap drive

We report a digitally-driven switching-mode amplifier using GaN devices in Voltage-Mode Class D operation, for use at 465 MHz (the recently designated frequency for LTE Band 31). The amplifier is fabricated as an integrated circuit including output devices and drivers. The output circuit employs two stacked GaN FETs; a bootstrap-drive configuration is used in order to increase the driver-stage efficiency for the uppermost GaN FET. The GaN VMCD amplifier achieves peak power-added efficiency of 66.6%, and an output power of 3.3W. At 6dB power backoff, power-added efficiency of 36.3% is achieved. These power-added efficiency values are the highest for reported GaN VMCD amplifiers at a commercial wireless frequency.

Integrating the Front End: A Highly Integrated RF Front End for High-SHF Wide-Band Massive MIMO in 5G

Fifth-generation (5G) mobile communications will need to accommodate huge traffic demands in the near future. Massive multipleinput/multiple-output (MIMO) technology utilizing hundreds of antenna elements has drawn attention as a key antenna configuration for envisioned 5G applications. Realizing the massive MIMO concept of active phased-array antennas (APAAs) for 5G will require small-size, low-power-consumption, and highly accurate phase control over the wide-band frequency range, which poses significant challenges for the RF front end. This article describes prototyped highly integrated RF front ends for high super-high-frequency (SHF) wide-band massive MIMO in 5G.

A highly integrated RF frontend module including Doherty PA, LNA and switch for high SHF wide-band massive MIMO in 5G

A highly integrated RF frontend module including a three-stage power amplifier (PA), a two-stage low noise amplifier (LNA) and a switch (SW) is presented for high SHF wide-band massive MIMO in 5G. In order to achieve efficient operation over wide-band frequency, Doherty PA configuration using a parasitic output capacitance neutralization technique is proposed for final stage PA. To improve LNAs gain flatness over wide frequency band, two R-LC stabilization circuits with different resonance frequencies are proposed. They are fabricated with 0.15-μm GaAs process, and integrated into a 5 × 5 mm2 QFN package. The state-of-the-art measured results show that final stage PA and three-stage PA achieve a drain efficiency (DE) at 8dB back-off of more than 22 % and 12 %, respectively, and a two-stage LNA achieves a noise figure (NF) of less than 1.4dB over 14.5–15.0 GHz.

Highly integrated RF frontend module for high SHF wide-band massive MIMO in 5G, and switching-mode amplifiers beyond 4G

In order to realize a massive MIMO concept, small size and low power consumption over the wide-band frequency range are challenges for RF frontends module. This paper describes a highly integrated RF frontend module for high SHF wide-band massive MIMO in 5G. The RF frontend module is designed with 0.15 µm GaAs process and assembled on 5 × 5 mm2 QFN package. By employing Doherty amplifier configuration using a parasitic output capacitance neutralization technique, it achieves low power consumption over wide frequency band. The integrated frontend architecture is an attractive solution for massive MIMO systems in 5G, and will contribute to 5G deployment. Additionally, the use of digital techniques is attractive future option beyond 4G (toward 5G), and amplifiers with them potentially lead to reduction of power consumption. Some prototyped switching-mode amplifiers are also presented.

Development of active phased array antenna for high SHF wideband massive MIMO in 5G

In the 5th generation mobile communication system, large system capacity, low latency and massive connection will be provided for novel and various applications. In order to realize these features, we are developing high SHF band massive-MIMO system which can secure wide system bandwidth and high spectral efficiency. Especially, the combination of analog beamforming (APAA: Active Phased Array Antenna) and digital MIMO signal processing for the multi-beam multiplexing is one of the promising approaches for reducing the complexity and power consumption. In this paper, hybrid beamforming configuration for high SHF band massive-MIMO system will be shown. Additionally the developed results of fundamental technologies such as array antenna panel and RF components are presented.

Linearity improvement method of fast-chirp signal for PLL by using frequency detector and division ratio modification

A linearity improvement method of a fast-chirp signal for a PLL by using a frequency detector and a division ratio modification is proposed. A fast-chirp signal generated by the PLL is distorted by its transient characteristic. The proposed method measures a frequency difference between the output and an ideal signal, and it modifies the division ratio of the PLL from the measurement result. An iteration of the modification of the division ratio in the proposed method enables higher linearity improvement. Experimental results show that the maximum frequency error decreases by 90.3% after 3 times of iteration compared to that without the proposed method. Measured chirp linearity L, which is defined as division of the maximum frequency error by a modulation speed is 93ns.

A 0.3-to-5.5 GHz Digital Frequency Discriminator IC with Time to Digital Converter

A 0.3 to 5.5 GHz range, 50ns-detection Digital Frequency Discriminator (DFD) using a Time to Digital Converter is presented. Wide frequency range and high accuracy are achieved by an averaging technique using all periods of the input signal and periodical number during the measurement time using TDC. The DFD, fabricated in 0.18-μm SiGe-BiCMOS, achieves measured absolute error below 0.39MHz and standard deviation below 1.53MHz-RMS during 50 ns detection time in the band from 0.3 GHz to 5.5 GHz.