Kenichi Tajima

Coherent homodyne receiver with a compensator of Doppler shifts for inter orbit optical communication

This paper presents Bread Board Model (BBM) of coherent homodyne receiver with an optical phase locked loop and a frequency compensator of Doppler shifts for inter satellite optical communication link. 2.5Gbps BPSK data has been demodulated with sensitivity of -49.1dBm at bit rate of 1e-6 under initial frequency offset of +/-7 GHz simulated as Doppler shifts due to variation of distance between each satellite.

Homodyne BPSK receiver with Doppler shift compensation for inter satellite optical communication

This paper presents Bread Board Model (BBM) of homodyne BPSK (Binary Phase Shift Keying) receiver with an optical phase locked loop and a Doppler shifts compensator for inter satellite optical communication link. 2.5Gbps BPSK data has been demodulated with sensitivity of −49.1dBm at bit error rate of 1e-6 under initial frequency offset of +/−7.5 GHz simulated as Doppler shifts due to relative motion of each satellite.

An X-band even harmonic type direct converter for CDMA satellite communications

This paper describes an X-band even harmonic type direct converter(EH-DC) used in earth stations for CDMA satellite communications. Technical features of this EH-DC are as follows: (a) Carrier leakage of a modulator is extremely low by employing an even harmonic mixer(EH-MIX). (b) High accuracy of a demodulator(low amplitude error and phase error) is achieved by employing an even harmonic quadrature mixer(EH-QMIX). (c) Automatic frequency control(AFC) function is realized by employing a PLL frequency synthesizer driven by a direct digital synthesizer(DDS) with Hz-order tuning. Experimental results in X-band indicate that the proposed EH-DC has no degradation of BER characteristics compared with a heterodyne type transceiver.

New suppression scheme of /sol Delta//spl Sigma/ fractional-N spurs for PLL synthesizers using analog phase detectors

This paper presents a new suppression scheme of ΔΣ fractional-N spurs for PLL synthesizers using analog phase detectors. The proposed scheme optimizes a phase difference of two phase-detector input signals to suppress spurious emissions caused by the ΔΣ fractional modulation. The phase difference is controlled by a preset signal for phase lock acquisition. The developed VHF-band ΔΣ fractional-N PLL synthesizer with a 2nd order MASH modulator suppresses the largest spurious level by 15dB using the proposed scheme.

Novel error correction memory compression technique of a DDS using the equi-section division method

This paper presents a novel memory compression technique for error correction of a direct digital synthesizer (DDS) using the equi-section division method. In the phase-to-amplitude converter (PAC) of the DDS, the sinusoidal phase data of a one-quarter period is divided into 2S equi-sections; then the equi-section type sine amplitude approximation (ESAA) is performed. An error correction memory is used to reduce error after the ESAA. In order to reduce the size of the error correction memory, we propose a phase adjustment technique to realize a shared memory. In this proposed technique, phase data which is equivalent to memory address is changed to optimum value in each section. To verify the proposed technique, we calculate the maximum spurious level at output of the PAC in the case of 8 sections. The maximum spurious level is −89.5 dBc. The proposed technique reduces the total size of memories to approximately 1/2S without affecting spurious levels.

Linearity improvement method of fast-chirp signal for PLL by using frequency detector and division ratio modification

A linearity improvement method of a fast-chirp signal for a PLL by using a frequency detector and a division ratio modification is proposed. A fast-chirp signal generated by the PLL is distorted by its transient characteristic. The proposed method measures a frequency difference between the output and an ideal signal, and it modifies the division ratio of the PLL from the measurement result. An iteration of the modification of the division ratio in the proposed method enables higher linearity improvement. Experimental results show that the maximum frequency error decreases by 90.3% after 3 times of iteration compared to that without the proposed method. Measured chirp linearity L, which is defined as division of the maximum frequency error by a modulation speed is 93ns.

A frequency synchronization scheme for time varying Doppler-shift compensation using the direct return signal

In this paper, a novel frequency synchronization scheme between platforms for a bistatic SAR is described. The proposed scheme uses the direct return signal to compensate a time varying Doppler-shift. The synchronization is established by using a PLL technique. And in a PFD of the PLL, the Doppler-shift of a reference signal for the PLL is canceled out by the Doppler-shift of the direct return signal. A detail analysis of the synchronization error for the proposed scheme is presented. Experimental results show that the proposed scheme achieves stable frequency synchronization between the platforms under the time varying Doppler-shift. And theoretical analysis and experimental results indicate that the synchronization error of 3.3×10-12 can be achieved in the assumed condition. This synchronization error is enough to satisfy the requirements for bistatic SARs.

Novel Phase-Continuous Frequency Hopping Control for a Direct Frequency Synthesizer Using a Quadrature Mixer Driven by Two DDSs

This paper presents novel phase-continuous frequency hopping (FH) control for a direct frequency synthesizer (DFS) using a quadrature mixer driven by two direct digital synthesizers (DDSs). To achieve wideband FH in both of the lower and the upper sidebands of a local frequency in a quadrature mixer, the proposed DFS decreases or increases the phase of DDS output signals corresponding to frequency offset from a local frequency of the quadrature mixer. To realize phase decrement, the proposed method adds a complement number in a phase accumulator of a DDS, while a conventional DDS does not use phase decrement but uses a switchable combiner. In addition, as the phase accumulator output changes continuously by summing phase increment, the proposed method always assures phase continuity of a DFS output signal, which ends up suppressing sidelobe level of frequency hopped signals. The calculation and measurement results indicate that a sidelobe of a signal spectrum using the proposed phase continuous method is approximately 10 dB better than that using a conventional phase discontinuous method.