Kenji Kawakami

A monolithic even harmonic quadrature mixer using a balance type 90 degree phase shifter for direct conversion receivers

This paper proposes a novel circuit configuration of an even harmonic quadrature mixer (EHQMIX) for direct conversion receivers. In this EHQMIX, a 90 degree phase shifter consists of balance type high pass and low pass filters, and it does not require any circuits connecting to the ground plane. So this configuration is suitable for low cost monolithic IC without any via-holes, because amplitude and phase imbalance caused by inductance included in wires and leads of a package for circuits to the ground plane can be reduced. A developed L-band MMIC achieves good quadrature detecting characteristics.This paper proposes a novel circuit configuration of an even harmonic quadrature mixer (EHQMIX) for direct conversion receivers. In this EHQMIX, a 90 degree phase shifter consists of balance type high pass and low pass filters, and it does not require any circuits connecting to the ground plane. So this configuration is suitable for low cost monolithic IC implementation without any via-holes, because amplitude and phase imbalance, caused by the inductance included in the wires and leads of a package, can be reduced for circuits connected to the ground plane. A developed L-band MMIC achieves good quadrature detection characteristics.

A 94 GHz high performance quadruple subharmonic mixer MMIC

A 94 GHz high performance quadruple subharmonic mixer (4/spl times/SHM) MMIC has been designed and fabricated for a down converter. The required LO frequency is only a quarter of RF frequency which is a half LO frequency of conventional double subharmonic mixers (2/spl times/SHM). The conversion gain and noise power were experimentally compared with that of a conventional subharmonic mixer. The quadruple subharmonic mixer showed the maximum conversion gain of -11.4 dB at an RF frequency of 94 GHz and a LO frequency of 23.5 GHz. The maximum noise power of -159 dBm/Hz was obtained at an IF frequency of 100 kHz. This noise measurement also suggests noise performance at low IF frequency depends not on the LO mixing frequency but on the 1/f noise of the Schottky barrier diode. The fabricated MMIC chip size is as small as 0.9 mm/spl times/1.4 mm. To our knowledge, these results are the best performances demonstrated from a quadruple subharmonic mixer MMIC in the W-band millimeter-wave range.

5.8 GHz high sensitivity rectenna array

This paper presents the 5.8 GHz high sensitivity rectenna array with advanced microstrip-type rectifiers and circularly patch antennas achieving a good balance between a high-efficiency and RF weak power operation. The fabricated rectenna element has achieved RF-DC conversion efficiency of 54% at input RF power of 1mW. Furthermore, we have proposed the novel structure which enhances robustness to the breakdown of the diodes when the rectenna elements are arrayed.

A Millimeter-Wave Highly Linear VCO MMIC with Compact Tuning Voltage Converter

This paper presents a fully integrated highly linear and low phase noise voltage controlled oscillator (VCO) with a novel compact tuning voltage converter for millimeter-wave applications. The tuning voltage converter consists of only a few diodes and resistors and has nonlinear characteristics to correct varactor tuning curves. The authors fabricated the millimeter-wave VCO MMIC employing InGaP/GaAs HBT process. The MMIC chip size is 2.55 mm times 1.4 mm, in contrast the voltage converter has the size of 0.35 mm times 0.70 mm. The measured tuning sensitivity of 97 plusmn12 MHz/V is achieved for voltages between 0 V and 5 V, and the temperature dependency is very small. Also the phase noise performance is -110.7 dBc/Hz at 1MHz offset from the carrier when the oscillation frequency is 38.2 GHz. This linearization technique can greatly reduce the configuration of the conventional software linearization system

A Ka-band direct oscillation HBT VCO MMIC with a parallel negative resistor circuit

This paper describes a low phase noise Ka-band VCO MMIC employing InGaP/GaAs HBT processes. The VCO has the following two features: a novel circuit comprising negative resistors arranged in parallel that achieves a steep phase slope, and a tuning circuit with two resonators that offers a wide tuning range and steep phase slope. Measurement results of the developed VCO show a phase noise ranging from -111 to -114 dBc/Hz at an offset frequency of 1 MHz, and a tuning bandwidth above 1.1 GHz in a 38-39 GHz band.

Unbalance effects of an antiparallel diode pair on the virtual local leakage in an even harmonic mixer

An even harmonic mixer (EHM) with an antiparallel diode pair (APDP) is an effective technique for low spurious transmitters especially in the millimeter-wave region, since APDP can suppress the virtual LO leakage that locates nearby a desired RF signal. The purpose of this study is to clarify unbalance effects of an APDP on the virtual local leakage. For this purpose, fundamental formulas are indicated in this paper. As a result of the analysis, two conclusions are given: (a) due to unbalance on parasitic resistance of the APDP, the virtual LO leakage is increased by increment of LO power; (b) due to unbalance on built-in voltage of the APDP, the virtual LO leakage is decreased by increment of LO power. Measured results indicate good agreement with presented formulas.

An X-band even harmonic type direct converter for CDMA satellite communications

This paper describes an X-band even harmonic type direct converter(EH-DC) used in earth stations for CDMA satellite communications. Technical features of this EH-DC are as follows: (a) Carrier leakage of a modulator is extremely low by employing an even harmonic mixer(EH-MIX). (b) High accuracy of a demodulator(low amplitude error and phase error) is achieved by employing an even harmonic quadrature mixer(EH-QMIX). (c) Automatic frequency control(AFC) function is realized by employing a PLL frequency synthesizer driven by a direct digital synthesizer(DDS) with Hz-order tuning. Experimental results in X-band indicate that the proposed EH-DC has no degradation of BER characteristics compared with a heterodyne type transceiver.

A 19 GHz low phase noise HFET VCO MMIC

A 19 GHz extremely low phase noise voltage controlled oscillator (VCO) MMIC is presented. To reduce the phase noise of the VCO, a heterostructure field effect transistor (HFET) is used as the active device, because its low frequency noise properties are superior to that of high electron mobility transistors (HEMT). This VCO showed a typical phase noise of -120 dBc/Hz at 1 MHz offset from the carrier. This performance is better than other VCOs operating above 10 GHz. The measured tuning range is 400 MHz and output power is 2 dBm. The fabricated MMIC chip size is 2.7 mm/spl times/1.4 mm.

Formulation of a Dual-Tapped Microstrip Resonator VCO

This paper provides a formulation of the dual-tapped microstrip resonator. The formulation derives the Q-factor of the resonator, and the maximum value of the Q-factor while still satisfying oscillation conditions. It is shown that the optimized Q-factor can be determined without changing the resonant frequency bandwidth. The phase-noise performance of a voltage-controlled oscillator (VCO) using a dual-tapped microstrip resonator can therefore be designed independent of the design of the oscillation bandwidth. This feature results in simple design of low phase-noise VCOs while maintaining the desired oscillation bandwidth. Experimental results of an X-band VCO employing the dual-tapped microstrip resonator verify the theoretical findings. The fabricated X-band VCO achieves an oscillation bandwidth of 11.86-12.09 GHz and phase noise lower than -114.4 dBc/Hz at 100-kHz offset from the carrier. This VCO is one of the most low phase-noise planar X-band VCOs published to date.

Novel error correction memory compression technique of a DDS using the equi-section division method

This paper presents a novel memory compression technique for error correction of a direct digital synthesizer (DDS) using the equi-section division method. In the phase-to-amplitude converter (PAC) of the DDS, the sinusoidal phase data of a one-quarter period is divided into 2S equi-sections; then the equi-section type sine amplitude approximation (ESAA) is performed. An error correction memory is used to reduce error after the ESAA. In order to reduce the size of the error correction memory, we propose a phase adjustment technique to realize a shared memory. In this proposed technique, phase data which is equivalent to memory address is changed to optimum value in each section. To verify the proposed technique, we calculate the maximum spurious level at output of the PAC in the case of 8 sections. The maximum spurious level is −89.5 dBc. The proposed technique reduces the total size of memories to approximately 1/2S without affecting spurious levels.