Hideyuki Sugita

On-chip transmission line for long global interconnects

This paper investigates the feasibility of differential transmission line interconnects. On-chip differential transmission lines achieve higher speed signal transmission and lower power consumption than RC lines at global interconnects. Differential transmission line interconnects are a key technology for breaking through the limitations of delay and power consumption at global interconnects in exchange for an increase in the interconnect layers.

4 Gbps On-Chip Interconnection using Differential Transmission Line

This paper demonstrates the differential transmission line interconnect for high-speed global interconnect IP. The interconnect is fabricated using a 180 nm CMOS technology. 4 Gbps signal transmission can be achieved in measurement results. The on-chip transmission line performs faster signal transmission than common RC interconnects

A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative

This paper demonstrates a low voltage differential signaling (LVDS)-type on-chip transmission line (TL) interconnect to solve delay issues on a global interconnect. The proposed TL interconnect can achieve 10 Gbps signaling with 2.7 mW power consumption. The on-chip LVDS TL interconnect has the best power efficiency for on-chip interconnects at over 1 mm. Delay variation of the TL interconnect is 89 % smaller than that of the conventional RC interconnect.

Zero-crosstalk bus line structure for global interconnects in Si ultra large scale integration

In this paper, we propose a novel technique for achieving high-density, high-speed and low-power on-chip bus lines using differential transmission lines. The feasibility of this technique is discussed with a two-dimensional electromagnetic simulator (Ansoft 2D Extractor) and time-domain measurements. Results show that the proposed bus line can transmit at over 12 Gbps. The proposed bus line can reduce wiring area by 30% compared with a conventional co-planar line.

Twisted differential transmission line structure for global interconnect in Si LSI

This paper investigates the twisted differential transmission line structure to achieve high-speed signal transmission and electromagnetic interference (EMI) noise reduction of global interconnects in Si LSIs. The differential transmission line in Si LSIs can transmit a 12 Gbps pulse signal and has the capability of reducing EMI noise. The proposed twisted-diagonal-pair line provides high-speed, low-EMI-noise, high-crosstalk-robustness and high-density global interconnects in Si LSIs.

High speed and low power on-chip micro network circuit with differential transmission line

This work presents a high speed and low power on-chip micro network circuit with differential transmission line for seamless intra- and inter-chip communication. A 4 Gbps pulse signal transmission was confirmed and an 8 Gbps pulse signal was confirmed at the receiver circuit in 0.35 /spl mu/m and 0.18 /spl mu/m CMOS process technologies, respectively. It is expected that over 10 Gbps signal transmission can be achieved by using sub-100 nm CMOS technologies. From the simulated results, the RLC differential transmission line is faster and has lower power consumption than the RC line.

Differential transmission line structure for over 10 Gbps signal transmission at global interconnect in Si ULSI

The diagonal-pair line structure is proposed as a differential transmission line, which achieves high speed and low power signal transmission in Si ULSI. This paper investigates transmission characteristics of the diagonal-pair line with time-domain measurements and electromagnetic simulations. 3 Gbps signal propagation can be achieved by one-cm-long diagonal-pair line, which is fabricated by 0.35 /spl mu/m CMOS process. Simulated results show that the proposed transmission line can transmit 30 Gbps signal.

Distributed constant passive devices using wafer-level chip scale package technology for one-chip wireless communication circuits

Large losses of on-chip passive devices are crucial problem for CMOS RF circuits. This paper proposes the use of wafer-level chip scale package (WL-CSP) technology to realize on-chip distributed-constant passive devices on Si CMOS substrates. In this paper, a 3 dB 90deg directional coupler using WL-CSP technology is investigated. Algebraic comparison of simulation results with measurement results are performed, which express the same tendency. The coupler has insertion loss of -0.5 dB, isolation of -29.8 dB and VSWR of 1.2 in the measurement results. The WL-CSP coupler has almost the same characteristics as those fabricated on GaAs and Al2O3 substrates. The WL-CSP technology contributes to realize low-loss RF passive devices on Si CMOS chip, which is indispensable to achieve small-size, low-price and low-power-consumption RF circuits

Zero-Crosstalk Bus Line Structure for Global Interconnects in Si ULSI

The International Technology Roadmap for Semiconductors has predicted that global interconnect delay becomes much larger than gate delay annually [1]. The global interconnects are conventionally designed as an RC line, and more repeaters are required for longer global interconnects [2]. Power consumption and delay time are proportional to a line length. It is a significant issue to reduce delay time and power consumption in global interconnects simultaneously. This paper proposes a novel technique to achieve high-speed signal transmission, low power consumption and high-density on-chip bus line using differential transmission lines (DTL). Generally, there is a trade-off between a wiring pitch and crosstalk robustness. We show the high-density bus line structure that can achieve zero crosstalk-noises. The feasibility of the proposed structure is discussed using results from a twodimensional electromagnetic simulator (2D Extractor, Ansoft) and a time-domain measurement.

Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology

This paper proposes high-Q distributed constant passive devices using wafer-level chip scale package (WL-CSP) technology, which can be realized on a Si CMOS chip. A 90° directional coupler using the WL-CSP technology has center frequency of 25.6 GHz, insertion loss of -0.5 dB and isolation of -29.8 dB in the measurement result. The WL-CSP technology contributes to realize low-loss RF passive devices on Si CMOS chip, which is indispensable to achieve small-size, cost-effective and low-power monolithic wireless communication circuits (MWCCs).