Kazuhisa Itoi

Si through-hole interconnections filled with Au-Sn solder by molten metal suction method

This paper deals with a fabrication method of conductive through-holes in a silicon substrate, which can be applied for micro electro-mechanical system (MEMS) devices or high-density packaging. The through-holes are formed by deep reactive ion etching (DRIE) and filled with Au-Sn solder by molten metal suction method (MMSM). The MMSM we have proposed is capable of filling high aspect ratio thorough-holes with conductive metal. We could make more than 18,000 conductive through-holes, 30 /spl mu/m in diameter and 300 /spl mu/m in depth, in a 4 inches sized silicon (Si) wafer. We report the principle of the filling, the fabrication processes and the structure of the through-hole interconnections.

Conductive interconnections through thick silicon substrates for 3D packaging

We have developed key technologies to form conductive interconnections through a thick silicon substrate, which are potentially applied for 3D device fabrication or packaging of optical MEMS devices. In this paper, we demonstrate to form metal filled Through-Holes (THs) in thick Silicon (Si) substrates (t=/spl sim/500 /spl mu/m) mainly using Photo Assisted Electro-Chemical Etching (PAECE) and Molten Metal Suctioned Method (MMSM). The THs that we experimentally made with these technologies had 15 /spl mu/m in the diameter and the aspect ratio of 35. And the maximum density was 500 THs/cm/sup 2/. The dielectric breakdown voltage of the THs was more than 500 V. In the result of a radioisotope leak test using Kr-85, the leakage rate of THs between the front and the back of the substrate was lower than the detection limit (1 /spl times/ 10/sup -15/ Pa/spl middot/m/sup 3//sec.).

On-Chip High-

In this paper, the authors propose an on-chip high-Q variable inductor embedded in wafer-level chip-scale package (WL-CSP). The variable inductor has a metal plate and a spiral inductor fabricated by the WL-CSP technology. The metal plate can be moved by a microelectromechanical systems (MEMS) actuator, and the inductance is varied according to the position of the metal plate. At the present time, the MEMS actuator has not been implemented yet. In this paper, the authors present a feasibility study on the proposed variable inductor. The inductor is evaluated with measurement results using a metal plate moved by a micromanipulator instead of the MEMS actuator. At 2 GHz, the measured inductance is varied from 4.80 to 2.27 nH, i.e., the variable ratio is 52.6%. The maximum value of quality factor is 50.1

Q

On-chip high-Q spiral inductors on Si substrate with thick resin layer have been fabricated. These inductors were fabricated by a thick Cu electroplated rerouting and separated more than 10 /spl mu/m from Si substrate by a thick resin layer. The inductance L of 5.2 and 4.9 nH with a quality factor Q of 18.1 and 27.5 were obtained for a 3.5 turn rectangle spiral inductor at 2 GHz in /spl rho/ of 4-6, 1k /spl Omega/cm, respectively. This technology is favorable for Si RF application to minimize the stray inductance from wire-bonding and reducing circuit resistance.

Variable Inductor Using Wafer-Level Chip-Scale Package Technology

We present a high-Q variable inductor using redistributed layers, whose inductance is of nH-order for GHz applications. The inductance can be varied by shielding the magnetic flux by means of a metal plate above the inductor. The metal plate is moved using a MEMS actuator. At 2 GHz, the measured inductance is varied from 4.80 nH to 2.27 nH, i.e., the variable range is 52.6%. The maximum value of quality factor is 50.1.

On-chip high-Q spiral Cu inductors embedded in wafer-level chip-scale package for silicon RF application

A linear magneto-impedance (MI) sensor integrated into a FePt thin film bias magnet which has in-plane isotropic magnetic property was investigated. The maximal bias field of 13.1 Oe was obtained after magnetizing a 1.3-mum thick FePt film in longitudinal direction of the sensor element. The bias field changed with the magnetizing angle. By controlling the angle in the magnetizing direction of the bias magnet and sensing direction, it was shown to be able to adjust the effective bias field after fabrication of the sensor element.

High-Q variable inductor using redistributed layers for Si RF circuits

On-chip high-Q spiral inductors on Si substrate embedded in WLP have been fabricated. These inductors consisted of a thick Cu electroplated rerouting to reduce electrical resistance and a thick resin layer to separate the inductors typically 20 /spl mu/m from Si substrate. The inductance L of 5.0 and 4.9 nH with the quality factor Q of 28.4 and 42.9 were obtained for a 3.5 turn rectangle spiral inductor at 2 GHz on the Si substrate, which had a resistivity of 4-6, 1k/spl Omega/cm, respectively. The R/sub Si/ in the assignment parameters for lumped RLC equivalent circuit by ADS denoted more than 5 k/spl Omega/ in a 3.5 turn. In addition, the measured results of Q, L and f/sub res/ corresponded well with the simulated values by HFSS and Sonnet. This technology realizes embedded high quality inductors in WLP.

Thin Film Magneto-Impedance Sensor Integrated Into

On-chip Cu solenoid inductors on Si substrate with thick resin layer have been fabricated. These inductors were fabricated by dual Cu electroplating layers and separated more than 10 /spl mu/m from Si substrate by thick resin layer. The self-resonance frequency of 17.7 and higher than 20 GHz with peak-Q of 18.5 and 24.2 were obtained for a 5 turn solenoid inductor in the resistivity of 4, 1k /spl Omega/cm, respectively. This technology realizes that high performance inductors are embedded in wafer-level chip-scale packages.

{\rm L}1_{0}

Large losses of on-chip passive devices are crucial problem for CMOS RF circuits. This paper proposes the use of wafer-level chip scale package (WL-CSP) technology to realize on-chip distributed-constant passive devices on Si CMOS substrates. In this paper, a 3 dB 90deg directional coupler using WL-CSP technology is investigated. Algebraic comparison of simulation results with measurement results are performed, which express the same tendency. The coupler has insertion loss of -0.5 dB, isolation of -29.8 dB and VSWR of 1.2 in the measurement results. The WL-CSP coupler has almost the same characteristics as those fabricated on GaAs and Al2O3 substrates. The WL-CSP technology contributes to realize low-loss RF passive devices on Si CMOS chip, which is indispensable to achieve small-size, low-price and low-power-consumption RF circuits

FePt Thin Film Bias Magnet

1Susumu Sadoshima, 1Satoshi Fukuda, 2Hiroyuki Ito, 3Kazuhisa Itoi, 3Masakazu Sato, 3Tatsuya Ito, 4Ryozo Yamauchi, 1Kenichi Okada, 1Noboru Ishihara, and 1Kazuya Masu 1Integrated Research Institute, Tokyo Institute of Technology 2Precision and Intelligence Laboratory, Tokyo Institute of Technology 4259-R2-17 Nagatsuta, Midori-ku, Yokohama, 226-8503 Japan. Tel: +81-45-924-5031, Fax: +81-45-924-5166, E-mail: paper@lsi.pi.titech.ac.jp 3Electron Device Laboratory, Fujikura Ltd. 1440 Mutsuzaki, Sakura, Chiba 285-8550, Japan 4Fujikura Ltd., 1-5-1 Kiba, Koto-ku, Tokyo 135-8512, Japan