Hideyuki Tomizawa

Optimization of pitch-split double patterning phoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

Optimization of pitch-split double patterning photoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

Evaluation of double-patterning techniques for advanced logic nodes

The development of Double-Patterning (DP) techniques continues to push forward aiming to extend the immersion based lithography below 36 nm half pitch. There are widespread efforts to make DP viable for further scaling of semiconductor devices. We have developed Develop/Etch/Develop/Etch (DE2) and Double-Expose-Track-Optimized (DETO) techniques for producing pitch-split patterns capable of supporting semiconductor devices for the 16 nm and 11 nm nodes. The IBM Alliance has established a DETO baseline, in collaboration with ASML, TEL, CNSE, and KLATencor, to evaluate the manufacturability of DETO by using commercially available resist systems. Presented in this paper are the long-term performance results of these systems relevant to defectivity, overlay, and CD uniformity.

A damage-free sapphire substrate removal process to realize highly manufacturable wafer-level white LED package

We proposed a novel wafer level chip scale package in which Laser Lift Off (LLO) was adopted for substrate removal. We confirmed that the LLO did not cause both mechanical and thermal damages into GaN layer.