Miyoko Shimada

Ta penetration into template-type porous low-k material during atomic layer deposition of TaN

Ta penetration into a planar template-type porous low-k film during atomic layer deposition of TaN has been investigated by evaluating relations between Ta penetration and number of deposition cycles, exposure time of Ta precursor per deposition cycle, substrate temperature, and porosity of the porous low-k. The precursors were pentakisdimethylaminotantalum [PDMAT:Ta(N(CH3)2)5] and NH3. The porous low-k was a methylsiloxane (MSX) whose pore size in the maximum distribution and porosity of the porous low-k were 0–1.9nm and 0%–47%. Depth profile of the Ta penetration was measured by transmission electron microscopy and energy dispersive x-ray spectroscopy. The amount of penetrated and the penetration depth depended on the porosity. It was found that the precursors penetrate into the MSX film dominantly by gas phase diffusion through pores connecting from the surface to the inside. Increased surface area of the MSX film due to the pores results in a depletion of precursor at the wafer edge, and that this dep...

Etch-Byproduct Pore Sealing for Atomic-Layer-Deposited-TaN Deposition on Porous Low-k Film

Porous low-k and ultrathin atomic-layer-deposited (ALD)-TaN are expected to be useful materials for Cu interconnects in ULSI devices of the 45-nm technology node and beyond. One problem with integrating these into the Cu interconnect is the Ta penetration which occurs during ALD-TaN deposition. In this work, we propose a novel pore-sealing technique using an etch-byproduct that is deposited on a sidewall of the pattern during reactive-ion-etching of the stopper under the porous low-k. It was found that the Ta penetration is completely prevented by the etch-byproduct if the cap insulator for the porous low-k is a SiC/SiO2 multilayer. Two levels of single-damascene Cu interconnects with ALD-TaN and porous low-k were successfully fabricated without the penetration, and good electrical characteristics were obtained for the interconnects.

Structural Studies of High-Performance Low-k Dielectric Materials Improved by Electron-Beam Curing

With the use of a newly developed electron beam (EB) curing process, an advanced methylsilsesquioxane (MSQ) low-k dielectric (LKD) film of k=2.9 was developed. It is noteworthy that the EB curing process can drastically improve the mechanical strength of LKD film and reduces the thermal budget without increasing the k value. The X-ray absorption fine structure (XAFS) study on the LKD was conducted to clarify the structural change upon EB curing. The structure of the film was compared with those of two different types of other MSQ films, the ladder-network structure and the random-network structure, and a chemical vapor deposition (CVD) film. The Si–O–Si bond angle and Si–O (Si–C) bond length were determined by fitting the Fourier transformed extended X-ray absorption fine structure (EXAFS) spectra. Si–O–Si bond angle of LKD film was found to be between those of the ladder and the random structure, which are 135° and 147°, respectively. The X-ray absorption near-edge structure (XANES) spectra of LKD film revealed two broad features corresponding to a mixture of the two structures. In contrast, Si–O–Si angles of the EB-cured LKD film and the CVD film were similar, and the XANES features of both films were almost identical with those of the random structure. The electronic structure as determined from XANES spectra was also discussed by comparing three-dimensional-linkage models obtained by ab initio calculations. We confirmed that the EB curing process of LKD film causes a drastic structural change. The change from the mixture of ladder and random structures to the completely random structure was caused by C–H bond breaking followed by the formation of new polymer-like clusters with C–C bonds.

Ultrathin pore-seal film by plasma enhanced chemical vapor deposition SiCH from tetramethylsilane

One important issue for integrating atomic layer deposition (ALD) TaN on a template type porous low-k film is penetration of Ta precursor into the pores. Deposition of a thin film on a patterned sidewall by plasma enhanced chemical vapor deposition (PECVD) is a candidate for pore sealing. We have examined PECVD-SiCH from tetramethylsilane [Si(CH3)4:4MS] as a pore sealant and compared it to PECVD-SiOC from 4MS∕CO2 and SiO2 from tetraethoxysilane [Si(OC2H5)4:TEOS]. ALD-TaN had an incubation time on a blanket SiCH, while it did not on a SiCH patterned wafer. The SiCH had the lowest deposition rate and the highest step coverage which enabled deposition of an ultrathin pore-sealing film as thin as 2nm. Damascene Cu interconnects fabricated by using ALD-TaN barrier metal and the ultrathin SiCH pore-seal demonstrated good electrical characteristics which successfully presented the increase in leakage current due to metal penetration, and it minimized the increase in line resistance by keeping the sealing layer thin.

High Performance Ultra Low-k (k=2.0/keff=2.4)/Cu Dual-Damascene Interconnect Technology with Self-Formed MnSixOy Barrier Layer for 32 nm-node

In order to realize the effective dielectric constant (k eff)=2.4 for 32 nm-node copper (Cu) dual-damascene (DD) interconnects, a spin-on-dielectric (SOD) SiOC (k=2.0) as the inter-level dielectric and plasma-induced damage restoration treatment were successfully demonstrated. It was obtained that good via resistance and stress-induced voiding (SiV) reliability. In addition, CoW-cap and thin SiC (k=3.5) and dual hard mask process using a metal layer was proposed to reduce the capacitance of dielectric diffusion barrier and protection layers in hybrid (PAr/SiOC) inter-layer dielectric (ILD) structure. As for the metallization, a self-formed MnSixOy barrier technology was applied in hybrid ILD structure. Drastic reduction of via resistance and excellent electromigration and SiV performance were obtained for the first time in hybrid ILD structure

Self-Formed Barrier Technology using CuMn Alloy Seed for Copper Dual-Damascene Interconnect with porous-SiOC/porous-PAr Hybrid Dielectric

Self-formed barrier technology using copper (Cu) manganese (Mn) alloy seed was applied for Cu dual-damascene interconnect with porous-SiOC/porous-PAr (k=2.3) hybrid dielectric for the first time. More than 90% yield for wiring and via-chain was obtained. 70% reduction in via resistance was confirmed compared with the conventional process. To estimate the moisture resistance property of self-formed barrier, via resistance change was measured with dummy density pattern. As the result, it was found that the resistance change ratio of via for self-formed barrier does not depend on the dummy density, probably due to the high moisture resistance property of self-formed oxide barrier. In addition, outgas at high temperature is found to be essential to form self-formed barrier for porous dielectric.

A fully integrated novel Wafer-Level LED package (WL2P) technology for extremely low-cost solid state lighting devices

Reduction of cost has become the most important challenge for solid state lighting. We proposed a novel Wafer-Level LED Packaging (WL2P) technology, which enables both extremely low cost and small size for future solid state lighting. Where a conventional package needs individual assembly steps, resulting in high fabrication cost, we carried out from growth of the GaN layer, over formation of Inter Layer Dielectric (ILD), wiring for solder pad to printing the phosphor layer on a whole wafer in our WL2P. Thus, for the first time a fully integrated wafer-level process was successfully applied to light emitting diode (LED) devices. It was clearly demonstrated that our WL2P has an excellent thermal resistance as low as 24.2K/W in the 0.6×0.3mm size prototype structure because of the direct connection of Cu wiring to the light emitting layer and a maximum injection power density was as high as 1157W/cm2 in a difference of 50°C between junction temperature and ambient temperature on the aluminum based printed wiring board (PCB)

3-dimensional structures of pores in low-k films observed by quantitative TEM tomograph and their impacts on penetration phenomena

3-dimensional structures of pores in porous low-k films have been quantitatively observed by transmission electron microscopy (TEM) tomographic technique for the first time. The 3-dimensional (3-D) reconstruction images clarified that the shape of pores are distorted and connectivity of the pores, such as open or close pores, depended on pore formation technique in the films, e.g. template or nano-clustering technique. Quantitative information of pores structure from 3-D reconstruction images were obtained using a 3-D structure analysis algorithm. The size of pores and connectivity influenced on metal penetration into the pores during atomic layer deposition (ALD) and chemical penetration which resulted in void formation in porous low-k films.

2-dimensional distribution of dielectric constants in patterned low-k structures by a nm-probe STEM/valence EELS (V-EELS) technique

2D distribution of dielectric constants or damage in porous low-k trench structures have been characterized with nm-order space resolution by valence electron energy loss spectroscopy (V-EELS) combined with scanning transmission electron microscopy (STEM) for the first time. Kramers-Kronig analysis (KKA) was carried out to estimate dielectric constants from V-EELS spectra. The results derived from the STEM/V-EELS technique showed that the dielectric constant at a side wall was higher than that at a central region in a trench patterned porous poly-methylsilsequioxane (MSQ) film. It is shown that the STEM/V-EELS technique combined with KKA is a unique technique to investigate changes in local structures and dielectric constants of low-k films, caused by such as plasma treatments, in fine structures.

Robust BEOL Process Integration with Ultra Low-k (k=2.0) Dielectric and Self-Formed MnO x Barrier Technology for 32 nm-node and beyond

Porous Low-k dielectric (k=2.0) was applied for Copper (Cu) dual-damascene interconnect with SiOC/PAr hybrid dielectric. More than 90% yield for via was obtained and approximately 5% capacitance reduction in inter-layer was obtained compared with the porous-SiOC/porous-PAr (k=2.3) hybrid dielectric process. The performance of stress-induced voiding was the same as for the conventional process. Meanwhile, with self-formed barrier process, more than 10 nm wider tolerances for misalignment was obtained compared with the conventional tantalum (Ta) barrier metal (BM) process, due to its thin barrier thickness and Cu-to-Cu connection for via and wiring.