Hideyuki Wada

Packaging technology for imager using through-hole interconnections in Si substrate

For high-density packaging of ICs or other devices, it is one of the essential technologies to form through-hole interconnections in a Si substrate that electric circuits are built on in advance. We have developed a fabrication technology of wafer-level-packaging (WLP) for imagers, using the through-hole interconnections from the backside of the Si substrate to the top. The package consists of a glass cap protecting an image sensing area on the top side, the through-hole interconnections as leads, the copper re-routing and solder bumps on the backside. All processes of the packaging were done at wafer level. This paper describes the fabrication process and evaluation results of the mechanical and electrical characteristics of the WLP for imagers.

Wafer-Level Packaging Technology With Through-Hole Interconnections in Silicon Substrate

An advanced packaging technology with through-hole interconnections, which enables miniaturization and high-density packaging of electronic devices including MEMS devices and optical devices, has been developed. In this work, through-hole interconnections were applied to an image sensor packaging. Through-holes, 80μm in diameter and 200μm in depth, were formed from backside of the device wafer by Deep Reactive Ion Etching (DRIE). After an insulation layer was formed inside the holes, conductive material such as copper (Cu) or Gold-Tin (Au-Sn) alloy solder was filled into the holes by electroplating method or Molten Metal Suction Method (MMSM). This technology enables wafer-level packaging of the image sensor device. Some electrical characteristics and reliability performances including electric resistance, breakdown voltage, high-temperature storage test, heat cycle test, temperature-humidity test were examined. In this paper, fabrication processes, structural and electrical characteristics and reliability of the package will be reported.Copyright