Hiraku Nakano

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custom integrated circuits conference | 1991

Hiraku Nakano; Masaitsu Nakajima; Yasuhiro Nakakura; Tadahiro Yoshida; Yoshiyuki Goi; Yuji Nakai; Reiji Segawa; Takeshi Kishida; Hiroshi Kadota

A 80-MFLOPS 64-bit microprocessor is described that employs superscalar architecture to execute two instructions, including the combination of 64-bit floating-point add and multiply instructions, in one 25-ns cycle simultaneously. The processor, implemented in a 0.8- mu m CMOS technology, contains 1300 K transistors. The processor also employs a RISC (reduced instruction set computer) architecture and Harvard-style bus organization. Division is accomplished every 200 ns. A typical performance is 64 MFLOPS.<<ETX>>

IEEE Journal of Solid-state Circuits | 1992

Hiraku Nakano; Masaitsu Nakajima; Yasuhiro Nakakura; Tadahiro Yoshida; Yoshiyuki Goi; Yuji Nakai; Reiji Segawa; Takeshi Kishida; Hiroshi Kadota

An 80-MFLOPS (peak) 64-b microprocessor that employs superscalar architecture to execute two instructions simultaneously in one 25-ns cycle, including the combination of 64-b floating-point add and multiply instructions, is described. The processor implemented in a 0.8- mu m CMOS technology contains 1300 K transistors. The processor also employs a RISC architecture and Harvard-style bus organization. The authors provide an overview of the processor, especially focusing on processor architecture, floating-point hardware, and performance. >

Archive | 1997