Yasuhiro Nakakura

A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit

A microprocessor designed as a processing element of a scientific parallel computer system is described. This chip consists of a simple integer processor core and dedicated floating-point hardware and executes 64-bit floating-point addition, subtraction, and multiplication at a rate of every 50 ns and division every 350 ns. The processor, which employs RISC architecture and Harvard-style bus organization, executes most of the 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology, containing 440K transistors in a 14.4*13.5-mm/sup 2/ die. The authors provide an overview of the processor, especially focusing on the functions for a parallel system, floating-point hardware, and the new divide algorithm. >

A 80 MFLOPS 64-bit microprocessor for parallel computer

A 80-MFLOPS 64-bit microprocessor is described that employs superscalar architecture to execute two instructions, including the combination of 64-bit floating-point add and multiply instructions, in one 25-ns cycle simultaneously. The processor, implemented in a 0.8- mu m CMOS technology, contains 1300 K transistors. The processor also employs a RISC (reduced instruction set computer) architecture and Harvard-style bus organization. Division is accomplished every 200 ns. A typical performance is 64 MFLOPS.<<ETX>>

An 80-MFLOPS (peak) 64-b microprocessor for parallel computer

An 80-MFLOPS (peak) 64-b microprocessor that employs superscalar architecture to execute two instructions simultaneously in one 25-ns cycle, including the combination of 64-b floating-point add and multiply instructions, is described. The processor implemented in a 0.8- mu m CMOS technology contains 1300 K transistors. The processor also employs a RISC architecture and Harvard-style bus organization. The authors provide an overview of the processor, especially focusing on processor architecture, floating-point hardware, and performance. >

Parallel computer ADENART—its architecture and application

A new parallel computer, ADENART (previously it was called ADENA,) for numerical applications has been developed. It is composed of 256 processing elements (:PEs) and interconnection networtcHXnet.) Each PE consists of a dedicated floating-point processor VLSI whose sustained performance is 10 MFLOPS, a communication controller VLSI and locally-distributed memories. The peak performance of the system is, therefore, 2.56GFLOPS. HXnet supports two types of efficient data-transfer modes; FAST mode and SLOW mode. Both of them are useful for various applications. The practical performance of ADENART system has been evaluated by several application programs. In partial differential equation solver, the system performance was measured as 475 MFLOPS.

An Area-Effective Cell-Based Channel Decoder LSI For a Digital Satellite TV Broadcasting

A new channel decoder LSI, which will be used in digital satellite TV broadcasting Set-Top Boxes, has been designed. This LSIs functions include AD/DA conversion, QPSK demodulating, Viterbi decoding, frame synchronization, convolutional deinterleaving, Reed-Solomon (RS) decoding, and descrambling. We use a new method for Viterbi Decoding called the Tracking Survivor State Information (TSSI) method, which not only reduces power consumption, but also solves the problem of increasing memory size. To reduce the size of RS decoder circuit, we used a three-stage-pipeline structure as well as designed a new architecture to realize Euclids algorithm. This device has been fabricated in a 0.35 µm 3-metal CMOS standard cell-based process and is composed of 670 K transistors. In this paper, we describe the TSSI method of the Viterbi Decoder and the Reed-Solomon Decoders new 3-stage pipeline architecture.