Hiroaki Nakaoka
Panasonic
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Publication
Featured researches published by Hiroaki Nakaoka.
Surface & Coatings Technology | 1996
Bunji Mizuno; Ichirou Nakayama; Michihiko Takase; Hiroaki Nakaoka; Masafumi Kubota
Very shallow and dense doping was realized by using the plasma doping method. This method was applied to fabricate diodes and MOS transistors with photo-resist as a mask material. This method is likely to be an alternative to ion implantation due to its properties of low energy and high throughput. The brief history of plasma doping is also reviewed.
IEEE Transactions on Electron Devices | 1995
Atsushi Hori; Akira Hiroki; Hiroaki Nakaoka; Mizuki Segawa; Takashi Hori
A novel SPI (Self-aligned Pocket Implantation) technology has been presented, which improves short channel characteristics without increasing junction capacitance. This technology features a localized pocket implantation using gate electrode and TiSi/sub 2/ film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentration in the well while maintaining high latch-up immunity. The SPI and the gate to drain overlapped structure such as LATID (Large-Angle-Tilt Implanted Drain) technology allow use of the ultra low impurity concentration in the channel region, resulting in higher saturation drain current at the same gate over-drive compared to conventional device. The carrier velocity reaches 8/spl times/10/sup 6/ cm/sec and subthreshold slope is less than 75 mV/dec, which can be explained by low impurity concentration in the channel and in the substrate. The small gate depletion layer capacitance of SPI MOSFET was estimated by C-V measurement, and it can explain high performance such as small subthreshold slope. On the other hand, the problem and the possibility of low supply voltage operation have been discussed, and it has been proposed that small subthreshold slope is prerequisite for low power device operated at low supply voltage. In addition, the drain junction capacitance of SPI is decreased by 65% for N-MOSFETs, and 69% for P-MOSFETs both compared with conventional devices. This technology yields an unloaded CMOS inverter of 48 psec delay time at the supply voltage of 1.5 V. >
The Japan Society of Applied Physics | 1995
B. Mizuno; Hiroaki Nakaoka; M. Takase; A. Hori; I. Nakayama; Mototsugu Ogura
1. lntroduction The ultra shallow doping for sub-tenth micron CMOS has been proposed by low energy ion implantationl ) and solid phase diffusion2). We have been further developing a practical method for obtaining ultra shallow doping profiles at near room temperature. This technology was named plasma doping3). The shallow doping methods must satisfy the following key items. 1) low energy for shallow junctions 2) high through-put for productivity and fabrication of densely concentraled layers 3) low temperature lo avoid photoresist damage and undesired boron diffusion 4) safety; if possible, un use of no toxic gas (for example BzHo)
Archive | 2004
Kazuichiro Itonaga; Akihiro Yamamoto; Hiroaki Nakaoka; Isao Miyanaga; Yoshinao Harada
Archive | 1993
Mizuki Segawa; Yoshiaki Kato; Hiroaki Nakaoka
Archive | 1996
Bunji Mizuno; Hiroaki Nakaoka; Michihiko Takase; Ichiro Nakayama
Archive | 2001
Yoshihisa Harada; Soichiro Itonaga; Isao Miyanaga; Hiroaki Nakaoka; Akihiro Yamamoto; 弘明 中岡; 佳尚 原田; 績 宮永; 明広 山本; 総一郎 糸長
Archive | 1997
Tokuhiko Tamaki; Tatsuo Sugiyama; Hiroaki Nakaoka
Archive | 1996
Bunji Mizuno; Hiroaki Nakaoka; Michihiko Takase; Ichiro Nakayama
Archive | 1996
Atsushi Hori; Hiroaki Nakaoka; Hiroyuki Umimoto; 弘明 中岡; 博之 海本