Mitsuo Yasuhira

10 nmf perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction with over 400°C high thermal tolerance by boron diffusion control

We have developed a perpendicular-anisotropy magnetic tunnel junction (p-MTJ) stack with CoFeB free layer and Co/Pt multilayer based synthetic ferrimagnetic (SyF) pinned layer that withstand annealing at a temperature up to 420°C (that compatible with CMOS BEOL process) by controlling boron diffusion. We demonstrated the 10 nmφ p-MTJ with double CoFeB/MgO interface tolerable against 400°C annealing which is a requisite building block for realization of high density spin transfer torque magnetic random access memory (STT-MRAM) in reduced dimensions.

Improvement of Thermal Tolerance of CoFeB–MgO Perpendicular-Anisotropy Magnetic Tunnel Junctions by Controlling Boron Composition

We investigated annealing temperature Ta dependence of tunnel magnetoresistance (TMR) ratio and magnetic properties for perpendicular-anisotropy (CoFe)100-XBX/MgO magnetic tunnel junctions (MTJs) with single (CoFe)100-XBX/MgO interface (s-MTJ) and double CoFeB-MgO interface (d-MTJ) structures with various boron compositions X. High TMR ratio over 100% was observed in the s-MTJ with X= 35 at.% after annealing at 360°C-400°C, whereas the s-MTJ with X = 30 at.% showed the degradation of TMR ratio with the increase of Ta above 360°C, resulting from the decrease of perpendicular anisotropy. The d-MTJ with X = 25 at.% maintained high TMR ratio up to Ta = 400°C owing to its higher perpendicular anisotropy compared with the s-MTJ. The difference of perpendicular anisotropy between the s-MTJ and the d-MTJ can be attributed to higher interfacial anisotropy together with lower saturation magnetization of the d-MTJs. The lower saturation magnetization is attributable to two MgO layers that suppress boron diffusion from CoFeB layers, which was verified by cross-sectional line analysis using electron energy-loss spectroscopy.

1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator for Improving Device Variation Tolerance

A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array design with a high-signal-margin reference generator circuit was developed to create high-density 1T1MTJ STT-MRAMs. To realize an appropriate STT-MRAM design, fluctuations in the memory cell characteristics were first measured using a 1-kbit STT-MRAM test chip. Based on these measurements, a reference generator and an STT-MRAM cell array architecture were proposed. This cell array was evaluated in terms of the signal margin for read operation and its tolerance to device variation by means of Monte-Carlo SPICE circuit simulations. The proposed design enables a 50% improvement in the signal margin compared with the conventional cell array circuit.

Effect of Boron and Fluorine Incorporation in SiON Gate Insulator with Optimized Nitrogen Profile

In this paper, the effects of boron and fluorine in the SiO2/Si interface region with the optimized nitrogen profile are described. Fluorine in the interface region has been found to terminate the interface states and improve negative bias temperature instability (NBTI). However, fluorine enhances the boron penetration. The ideal nitrogen profile has been achieved in order to suppress NBTI characteristics by applying the SiN/SiO2 stack structure.

Effect of Fluorine on Interface Characteristics in Low-Temperature CMIS Process with HfO2 Metal Gate Stacks

In this paper, the effects of fluorine into HfO2 interface region by a low-temperature process are described. The new process for incorporating fluorine in the interface region has been optimized, and it has been found that fluorine terminates the interface defect. As a consequence, an ideal interface has been realized, which improves the negative bias temperature instability (NBTI) in metal gate electrode devices fabricated by the low-temperature process.

Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip

To realize a high-density spin-transfer-torque magnetic random access memory (STT-MRAM) device comparable with a current dynamic random access memory (DRAM) device, it is a key to develop a new technology for memory cell size reduction. We have already reported a chemical- mechanical-polishing(CMP)-based preparation technology for magnetic tunnel junctions (MTJs) above the via holes that can drastically reduce memory cell area. In this paper, we first introduce the MTJ preparation technology to the mega-bit class STT-MRAM test chip, and demonstrate the improvement of memory-cell operation yield.

Origin of variation of shift field via annealing at 400°C in a perpendicular-anisotropy magnetic tunnel junction with [Co/Pt]-multilayers based synthetic ferrimagnetic reference layer

We investigated properties of perpendicular-anisotropy magnetic tunnel junctions (p-MTJs) with [Co/Pt]-multilayer based synthetic ferrimagnetic reference (SyF) layer at elevated annealing temperature Ta from 350°C to 400°C. Shift field HS defined as center field of minor resistance versus magnetic field curve of the MTJs increased with increase of Ta from 350°C to 400°C. The variation of HS is attributed to the variation of saturation magnetic moment in the SyF reference layer. Cross sectional energy dispersive X-ray spectroscopy analysis revealed that Fe element of CoFeB in the reference layer diffuses to Co/Pt multilayers in the SyF reference layer.

Impact of sputtering condition for tungsten on magnetic and transport properties of magnetic tunneling junction with CoFeB/W/CoFeB free layer

Spin-transfer-torque magnetoresistive random access memories using CoFeB-MgO based magnetic tunnel junctions with perpendicular easy axis (p-MTJs) are attracting much attention owing to their high potential in offering electronics with both low-power-consumption and high-performance [1–3].

The influence of silicon nitride cap on NBTI and fermi pinning in HfO 2 gate stacks

In this paper, we report the improvements in the interfacial reaction between the gate dielectric and the gate electrode by adding SiN cap layer on HfO/sub 2/. We also report the drastic improvements in the gate leakage, V/sub th/ shift and NBTI.