Atsushi Hori

Quarter-micrometer SPI (Self-aligned Pocket Implantation) MOSFET's and its application for low supply voltage operation

A novel SPI (Self-aligned Pocket Implantation) technology has been presented, which improves short channel characteristics without increasing junction capacitance. This technology features a localized pocket implantation using gate electrode and TiSi/sub 2/ film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentration in the well while maintaining high latch-up immunity. The SPI and the gate to drain overlapped structure such as LATID (Large-Angle-Tilt Implanted Drain) technology allow use of the ultra low impurity concentration in the channel region, resulting in higher saturation drain current at the same gate over-drive compared to conventional device. The carrier velocity reaches 8/spl times/10/sup 6/ cm/sec and subthreshold slope is less than 75 mV/dec, which can be explained by low impurity concentration in the channel and in the substrate. The small gate depletion layer capacitance of SPI MOSFET was estimated by C-V measurement, and it can explain high performance such as small subthreshold slope. On the other hand, the problem and the possibility of low supply voltage operation have been discussed, and it has been proposed that small subthreshold slope is prerequisite for low power device operated at low supply voltage. In addition, the drain junction capacitance of SPI is decreased by 65% for N-MOSFETs, and 69% for P-MOSFETs both compared with conventional devices. This technology yields an unloaded CMOS inverter of 48 psec delay time at the supply voltage of 1.5 V. >

A self-aligned pocket implantation (SPI) technology for 0.2- mu m dual-gate CMOS

The self-aligned pocket implantation (SPI) technology developed features a localized pocket implantation using a gate electrode and TiSi/sub 2/ films as self-aligned masks. This process provides high punchthrough resistance and high current driving capability while suppressing the impurity concentration in the twin well. The drain junction capacitance is decreased by 30% for N-MOSFETs and by 49% for P-MOSFETs, compared to conventional LDD devices. It is found that a dual-gate CMOS device fabricated by the SPI technology achieves high circuit performance.<<ETX>>

High-performance dual-gate CMOS utilizing a novel self-aligned pocket implantation (SPI) technology

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi/sub 2/ film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length L/sub g/ (the physical gate length) is 0.21 mu m for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21- mu m gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5*10/sup 16/ cm/sup -3/). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 mu m, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 mu m. >

Experimental Study of Impact Ionization Phenomena in Sub- 0.1 µm Si Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs)

Impact ionization phenomenon in sub-0.1 μm Si metal-oxide-semiconductor field effect transistors (MOSFETs) has been examined in detail. N-MOSFETs with gate oxide of 4, 6 and 8 nm thickness were fabricated using pocket implantation technology. The test devices have n + polysilicon gate electrodes and shallow extension formed by arsenic implantation at the acceleration voltage of 15 keV. Sub-band-gap impact ionization can be observed for the 0.08 μm N-MOSFET. It is clearly observed that thin gate oxide suppresses impact ionization. Simulation results reveal that the lateral electric field near the drain is decreased by thinner gate oxide of 4 nm thickness. In addition, the dependence of the impact ionization rate on the gate oxide thickness decreases with decreasing gate length.