Hirohisa Gambe

A High Performance LSI Digital Signal Processor for Communication

This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSPs. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described in some detail.

A line terminating LSI using echo cancelling method for ISDN subscriber loop transition

A 144-kb/s digital subscriber loop (DSL) transmission system based on hybrid transmission with an echo cancelling method is described. It incorporates advanced LSI technology to obtain compactness, low cost, and high reliability. An echo canceller (EC) LSI has been developed using CMOS technology. Combined with the multiplexing processor (MXP) LSI, the EC LSI provides basic DSL equipment functions. A specially arranged frame format with a newly developed digital phase-locked loop (DPLL) circuit for stable timing extraction, an automatic balancing network, and a two-stage echo canceller characterize the system. Using this line termination circuit, the DSL equipment showed a reach of over 6 km when used with 0.5 mm diameter cable for 160-kb/s bidirectional digital transmission. >

An approach to LSI implementation of a 2B1Q coded echo canceler for ISDN subscriber loop transmission

An approach to large scale integration (LSI) implementation of the 2B1Q echo canceler for an integrated services digital network (ISDN) basic access interface is described. A hybrid architecture, using both analog and digital processing, is adopted for LSI implementation with a moderate circuit scale. Techniques using baud-rate sampling, such as square root f automatic gain control (AGC) equalization by power detection, timing extraction by peak estimation and a two-stage echo canceler with divided tables, are introduced to the system. Performance characteristics are also confirmed by computer simulation and a prototype system.<<ETX>>

On the Design of a High-Performance LSI Circuit Digital Signal Processor for Communication

This paper describes the design of a highly efficient CMOS LSI circuit digital signal processor (FDSP3). To realize an operating cycle rate of 10 MHz and a throughput rate of 0.6 μs per second-order filter section, considerable care has been paid to the design of software structures and hardware circuitry. Basic program routines and some application examples are also shown. These examples illustrate the high efficiency of the developed DSP device.