Toshitaka Tsuda

Optical MEMS for photonic switching-compact and stable optical crossconnect switches for simple, fast, and flexible wavelength applications in recent photonic networks

We review the development trends and state-of-the-art technologies of large-port-count optical switches over the past decade. Practical implementation of optical switch fabrics is discussed in terms of optical switch architectures, optical configurations, port counts, switch elements, and so on. We describe compact and stable optical crossconnect three-dimensional microelectromechanical systems (3-D-MEMS) switches that are a key technology in recent photonic networks. To show how these enable simple, fast, and flexible wavelength applications in the photonic layer, we discuss the fast and stable MEMS switching by novel comb actuator and V-shaped torsion bar, compact optical configuration with roof-type mirror, stable switch housing with cubic structure, packaging techniques by tolerance expansion and simple procedures of the component assembly, MEMS mirror controller with fast and low power digital notch circuit, reliability by shock absorption, and field trials. In addition, we discuss the impact of these switches on system integration for recent metropolitan area networks and enterprise networks.

Digital TDM-FDM Translator with Multistage Structure

In this paper, a new digital signal processing algorithm for the digital TDM-FDM translator is proposed. The digital TDM-FDM translator, which performs a direct translation between two multiplex formats in the telephone network (time-division-multiplexing (TDM) and frequency-division-multiplexing (FDM)) by using digital techniques, has advantages in accuracy and stability of characteristics over equivalent analog equipments. However from the economical point of view, it largely depends on the cost reduction of semiconductor devices and LSI technologies. The proposed algorthm can be realized using only two digital filters and does not require product modulators or Fast Fourier Transform (FFT) processors. The required number of multiplications, which is closely related to the quantity of hardware, is considerably reduced by the multistage structure of this algorithm. The reduction in the kind of required digital hardware and the required number of multiplications makes it possible to efficiently utilize the new hardware realization techniques of digital filters or multipliers using read-only memories and simple logic devices. Since it is foreseen that cost reduction of memory devices will be more rapid than that of logic devices, the proposed algorithm is expected to be advantageous with regard to cost over existing algorithms where complex multiplier logic is required. The estimation of the computation rate is carried out with reference to a practical case. The computer simulation results are also shown.

Experimental Bidirectional Subscriber Loop Transmission System

This paper describes a complete hardware implementation of an experimental two-wire digital subscriber loop transmission system using balanced pairs of wires. It is based on the time division burst mode transmission scheme (ping-pong), and provides two information channels, 64 kbits/s and 8 kbits/s, and a signaling channel both ways. The burst cycle is 2 ms and line transmission rate is 192 kbits/s. The salient feature of the system is that it is equipped with a powerful bridged tap equalizer which has the capability to compensate a large fraction of existing two-wire subscriber loops in Japan. It is realized by a fifth-order recursive filter using analog tapped delay lines, and a modified zero forcing algorithm is adopted for the adaptation of the tap coefficients. The experimental results showed that the combination of the \sqrt{f} AGC and the bridged tap equalizer enables the digital transmission up to 4 km on the 0.4 mm φ subscriber line with three bridged taps each of 400 m length.

An Approach to Multi-Service Subscriber Loop System Using Packetized Voice/Data Terminals

A new subscriber communication system and its design philosophy are described. In addition to telephone communication, the system is simultaneously able to offer data communication, still picture communication, etc. The system is composed of a packetized voice/data terminal, a multi-service switching equipment and the digital subscriber loop connecting between them. The system utilizes the existing subscriber line efficiently and is entirely suitable for coming telephone and data public digital network. 64 kbit/s PCM coded voice conversation and 48 kbit/s data communication were achieved simultaneously over 96 kbit/s digital subscriber line which was spanned up to 2 km.

LSI Processor for Digital Signal Processing and Its Application to 4800 Bit/s Modem

This paper describes a fast data processing LSI unit tailored to the digital signal processing (DSP) applications in the field of electrical communications. The results of successful application to the 4800 bit/s modem are also given. The LSI processor discussed here adopts a firmware control scheme to enhance the flexibility and freedom of application and extensively utilizes the pipeline processing technique to attain high speed data handling capability. The various operations encountered in DSP systems are unified into one operation of the type A \times B + C \rightarrow D and the LSI processor is designed to continuously perform this operation, while the data to be operated are transferred sequentially into the processor controlled by exterior firmware. The developed LSI handles 8 bit data at the clock frequency of 1.152 MHz and manages 144 K operations per second (6.9 μs cycle time). The LSI is an N-MOS chip containing 1500 gates and packaged in a 40 pin DIP. The automatic equalizer for 4800 bit/s modem was implemented using two of the developed LSI processors and about 4 K ROM and 1 K RAM memory chips. The measurement on this modem gave the error rate of 10-5at S/N = 17.6 dB and error free phase jitter allowance of 55° p-p. Application of the LSI processor to digital filters for roll-off spectrum shaping and timing signal extraction is also described.

A line terminating LSI using echo cancelling method for ISDN subscriber loop transition

A 144-kb/s digital subscriber loop (DSL) transmission system based on hybrid transmission with an echo cancelling method is described. It incorporates advanced LSI technology to obtain compactness, low cost, and high reliability. An echo canceller (EC) LSI has been developed using CMOS technology. Combined with the multiplexing processor (MXP) LSI, the EC LSI provides basic DSL equipment functions. A specially arranged frame format with a newly developed digital phase-locked loop (DPLL) circuit for stable timing extraction, an automatic balancing network, and a two-stage echo canceller characterize the system. Using this line termination circuit, the DSL equipment showed a reach of over 6 km when used with 0.5 mm diameter cable for 160-kb/s bidirectional digital transmission. >

An approach to LSI implementation of a 2B1Q coded echo canceler for ISDN subscriber loop transmission

An approach to large scale integration (LSI) implementation of the 2B1Q echo canceler for an integrated services digital network (ISDN) basic access interface is described. A hybrid architecture, using both analog and digital processing, is adopted for LSI implementation with a moderate circuit scale. Techniques using baud-rate sampling, such as square root f automatic gain control (AGC) equalization by power detection, timing extraction by peak estimation and a two-stage echo canceler with divided tables, are introduced to the system. Performance characteristics are also confirmed by computer simulation and a prototype system.<<ETX>>

Optical MEMS for photonic switching

Optical communication system is moving from WDM pipe to photonic network, where optical switching is requested as key functionality. This presentation reviews the current trend of photonic network, and how MEMS optical switch is being deployed, with some explanation of our optical MEMS switch.

CMOS LSI DSP and its application to voice band signals

This paper describes a newly developed CMOS LSI DSP and its application to a 32 Kbps ADPCM CODEC and a 4,800 bps data MODEM. The paper first analizes the required memory capacities of ROM and RAM as a function of arithmatic operation capability of DSP. Based on the results, the LSI DSP is developed, which has a proper amount of memory capacities. It has a multiplier which operates at a rate of 1.4 M operations/s. It is also equipped with a versatile I/O interface circuit which is suitable for multi-processors configuration of a system.

The Photonic Technologies Impact on the Next Generation Network

This paper describes the possible impact of photonic technologies on the next-generation network. With the explosion of the Internet (IP), the capacity demand is increasing exponentially, which exceeds Moors law. The next-generation IP network should sustain this increase. This paper shows the possible node processing bottleneck even the transmission capacity can be supported by the use of WDM technology. Based on this analysis, the paper proposes a virtual router network as a solution, which applies a logical full-mesh connection based on salient features of photonic network technology. Development of the WDM technology sets the target at 1000 wavelengths on a fiber so that a dynamic wavelength routing function is becoming available. The increase in wavelengths, transparency among wavelengths, and the wavelength routing function can provide an optical path, which forms the base of a logical full-mesh structure and also provides an easy migration scenario from the current network to the next-generation IP network. The possibility is examined by calculation using a bi-directionalloop network as an example. As the foundation of the proposal, the current statusof photonic network technologies is described with future projection.