Hiroki Kasai

Progress of FD-SOI technology for monolithic pixel detectors

We have been developing the 0.2 μm fully-depleted Silicon On Insulator (SOl) CMOS technology for monolithic pixel detectors. In order to improve the sensors sensitivity, 8 inch FZ wafer is introduced for handle substrate in SO! wafer. Stitching technology is also developed to get large detector chip area. Furthermore, nested well structure for the p-n junction and double-SOI structure are investigating for reducing the radiation damage and crosstalk between electrical circuitry in top silicon layer and sensors at substrate. In this document, recent progress of process technology for pixel detector is described.

Super steep subthreshold slope PN-body tied SOI FET with ultra low drain voltage down to 0.1V

We propose and demonstrate a super steep Subthreshold Slope (SS) new type SOI FET with a PN-body tied structure. It has a symmetry source and drain (S/D) structure. The device shows a super steep SS (<;6mV/dec) over 3 decades of the drain current with an ultralow drain voltage down to 0.1V. It also shows a low leakage current (below 1pA/um), a good Id-Vd characteristic and a negligible hysteresis characteristic.

Analysis of Effective Gate Length Modulation by X-Ray Irradiation for Fully Depleted SOI p-MOSFETs

An X-ray irradiation degradation mechanism has been investigated for fully depleted-silicon-on-insulator (FD-SOI) p-channel MOSFETs (p-MOSFETs). It is found that the drain current degradation by the X-ray irradiation has gate length dependence showing 20% degradation for L = 0.2 μm, while 8% for L = 10 μm after the 1.4 kGy(Si) X-ray irradiation. Using Teradas method, it was found that the degradation is not due to mobility degradation but due to radiation-induced gate length modulation (RIGLEM) and the associated increase of source and drain parasitic resistance. The major cause of degradation induced by the RIGLEM is explained by an analytical model, assuming a positive charge generation in sidewall spacers. It can be suggested that the X-ray irradiation degradation of FD-SOI p-MOSFET can be improved by optimizing the lightly doped drain region.

Total ionization damage effects in double silicon-on-Insulator devices

We are developing monolithic pixel sensors based on a 0.2 μm fully-depleted silicon-on-Insulator (SOI) technology. The major issue in applications them in high-radiation environments is the total ionization damage (TID) effects. The effects are rather substantial in the SOI devices since the transistors are enclosed in the oxide layers where generated holes are trapped and affect the operation of the near-by transistors. The double SOI sensors that provide an independent electrode underneath the buried oxide layer have been developed. We have irradiated transistor test elements and pixel sensors with γ-rays. By adjusting the potential of this electrode, the TID effects are shown to be compensated. The pixel sensor irradiated to 20 kGy recovered its functionality by applying a bias to the electrode. The radiation tolerance of the SOI devices has been substantially improved by the double SOI.

Total Ionization Damage Compensations in Double Silicon-on-Insulator Pixel Sensors

Shunsuke HONDA∗A, Kazuhiko HARAA, Kohei TSUCHIDAA, Mari ASANOA, Naoshi TOBITAA, Tatsuya MAEDAA, Yasuo ARAIB, Toshinobu MIYOSHIB, Takeshi TSURUC, Morifumi OHNOD, Noriyuki MIURAE, Hiroki KASAIE, Masao OKIHARAF A University of Tsukuba B High Energy Accelerator Research Organization (KEK) C Kyoto University D National Institute of Advanced Industrial Science and Technology (AIST) E Lapis Semiconductor Miyagi Co., Ltd. F Lapis Semiconductor Co., Ltd. E-mail: honda@hep.px.tsukuba.ac.jp

Tradeoff Between Low-Power Operation and Radiation Hardness of Fully Depleted SOI pMOSFET by Changing LDD Conditions

The interrelation between off-leakage as consideration of low-power operation and X-ray radiation hardness has been evaluated in view of optimizing the lightly doped drain (LDD) concentration of fully depleted silicon-on-insulator pMOSFET. The MOSFET with relatively low LDD concentration called ultralow-power P channel LDD (ULP-PLDD) shows a lower off-leakage of 0.1 pA/μm but limited X-ray radiation tolerance, such that the drain current is reduced by ~80% after 112-kGy(Si) X-ray irradiation due to radiation-induced gate length modulation (RIGLEM), while the MOSFET with six times higher LDD concentration called radiation-hardened PLDD (RH-PLDD) shows much higher radiation tolerance that the drain current reduction is ~20% for the same radiation dose because of RIGLEM improvement by the elimination of the offset structure employed in ULP-PLDD. The off-leakage of RH-PLDD is one order of magnitude higher than that of ULP-PLDD as <;1 pA/μm. It is shown that there is such a tradeoff between low-power operation and radiation hardness.