Morifumi Ohno

Monolithic Pixel Detector in a 0.15 μm SOI Technology

We describe a new pixel detector development project using a 0.15 μm fully-depleted CMOS SOI (silicon-on-insulator) technology. Additional processing steps for creating substrate implants and contacts to form sensor and electrode connections were developed for this SOI process. A diode test element group and several test chips have been fabricated and evaluated. The pixel detectors are successfully operated and first images are taken and sensibility to β-rays is confirmed. Back gate effects on the top circuits are observed and discussed.

Relationship between Nitrogen Profile and Reliability of Heavily Oxynitrided Tunnel Oxide Films for Flash Electrically Erasable and Programmable ROMs

A larger charge-to-breakdown value and much less threshold-voltage narrowing in the endurance properties of flash electrically erasable and programmable ROMs were achieved by incorporating a greater amount of nitrogen (∼ 10 21 atoms/cm 3 ) into the bulk of thin oxide films, as well as near the oxide/Si interface. The charge to breakdown value of thin oxide films formed under an optimized heavy oxynitride condition (dry oxidation at 1100°C; NH 3 annealing at 1000 °C for 30 s; N 2 O annealing at 1100°C for 30 s) was four times as large as that of a conventional dry oxide film. These results were attributed to the suppression of stress-induced charge traps and the interface state, due to the introduction of nitrogen atoms in the oxide bulk, as well as at the oxide/Si interface

SOI pixel developments in a 0.15μm technology

While the SOI (silicon-on-insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and low-power applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of fully-depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15mm FD-SOI CMOS process. We have preformed two multi project wafer (MPW) runs using this SOI process. We hosted the second MPW run and invited foreign universities and laboratories to join this MPW run in addition to Japanese universities and laboratories. Features of these SOI devices and experiences with SOI pixel development are presented.

Radiation resistance of SOI pixel devices fabricated with OKI 0.15μm FD-SOI technology

Silicon-on-insulator (SOI) technology is being investigated for monolithic pixel device fabrication. The SOI wafers by UNIBOND allow the silicon resistivity to be optimized separately for the electronics and detector parts. We have fabricated pixel detectors using fully depleted SOI (FD-SOI) technology provided by OKI Semiconductor Co. Ltd. The first pixel devices consisting of 32×32 pixels each with 20 μm square were irradiated with 60Co γ’s up to 0.60 MGy and with 70-MeV protons up to 1.3×1016 1-MeV n eq /cm2. The performance characterization was made on the electronics part and as a general detector from the response to RESET signals and to laser. The electronics operation was affected by radiation-induced charge accumulation in the oxide layers. Detailed evaluation using transistor test structures was separately carried out with covering a wider range of radiation level (0.12 kGy to 5.1 MGy) with 60Co γ’s.

Improvement of crystallinity of epitaxial Si1−xGex films with SiH4 treatment in in-situ rapid thermal chemical vapor deposition

Improvements in the crystallinity of epitaxial Si1−xGex films have been investigated by treating Si substrates with SiH4 in rapid thermal chemical vapor deposition (RTCVD) to bring this technology close to manufacture. It is found that the epitaxial Si layer formed during the SiH4 treatment just before Si1−xGex deposition is effective for improving the crystal quality of epitaxial Si1−xGex films. This method is seen as a promising technology for realizing heterostructural devices using Si1−xGex films.

Effectiveness of N/sub 2/O-nitrided gate oxide for high-performance CMOSFETs

Summary form only given. High-quality thin SiO/sub 2/ films are strongly needed for advanced integrated circuits such as CMOSFETs and EEPROMs. It is found that N/sub 2/O-nitrided SiO/sub 2/ film is more useful than NH/sub 3/-nitrided SiO/sub 2/ or pure SiO/sub 2/ film for obtaining high-performance CMOSFETs. However, the mechanism of hot-carrier degradation of CMOSFETs with these oxide films has not been discussed. A detailed study is reported on hot-carrier-induced degradation phenomena in nitrided SiO/sub 2/ gate CMOSFETs. It is confirmed that N atoms in gate oxide films prevent the generation of interface traps for NMOSFETs and H atoms accelerate electron trapping for PMOSFETs. Therefore, N/sub 2/O-nitrided gate oxide film free from H atoms is effective for obtaining high-performance CMOSFETs. >