Hiromasa Nakajima

A MPEG4 programmable codec DSP with an embedded pre/post-processing engine

We have developed a programmable DSP for MPEG4, H.263, H.261 and wavelet based sub-band codec algorithms. This DSP has the capability of processing these algorithms in real-time and has excellent flexibility, so that it can, for instance, perform video codec at 15 CIF frames/sec or video/speech (G.723.1) codec at 30 QCIF frames/sec. This chip includes a video pre/post-processing engine and needs only one 16 Mbit SDRAM as an external memory to perform the above algorithms, making it possible to realize low-cost systems. This chip is fabricated using 0.25 um CMOS technology and contains 7.7 M transistors on 9.41 mm/spl times/9.22 mm die.

A DSP for DCT-based and wavelet-based video codecs for consumer applications

We have developed a video digital signal processor (VDSP1) which performs real-time encoding and decoding for discrete cosine transform- (DCT-) based algorithms such as ITU-T H.261, H.263 and wavelet-based subband encoding algorithms. This LSI is suitable for consumer applications, as it was implemented using 0.5 /spl mu/m CMOS process technology to realize compactness (one million transistors on 65 mm/sup 2/) and low power (maximum: 560 mW). It features a processing unit which performs wavelet filtering at high speeds, a compact DCT circuit, and a fast, flexible DRAM interface for low-cost systems. At 40 MHz, a single chip is capable of processing quarter common intermediate format (QCIF) (176/spl times/144 pixels) size pictures at a rate greater than 15 frames/s.