Hiromitsu Hada

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 mu m/sup 2/. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm/sup 2/. >

A 90nm 12ns 32Mb 2T1MTJ MRAM

Since MRAM cells have unlimited write endurance, they can be used as substitutes for DRAMs or SRAMs. MRAMs in electronic appliances enhance their convenience and energy efficiency because data in MRAMs are nonvolatile and retained even in the power-off state. Therefore, 2 to 16Mb standalone MRAMs have been developed [1–4]. However, in terms of their random-access times, they are not enough fast (25ns) [1] as substitutes for all kinds of stand-alone DRAMs or SRAMs. To attain a standalone MRAM with both a fast random-access time and a large capacity, we adopt a cell structure with 2 transistors and 1 magnetic tunneling junction (2T1MTJ), which we previously published for a 1Mb embedded MRAM macro [5]. We need to develop circuit schemes to achieve a larger memory capacity and a higher cell-occupation ratio with small access-time degradation. We describe the circuit schemes of a 32Mb MRAM, which enable 63% cell occupation ratio and 12ns access time.

Resistance Controllability of

The controllability of resistance in the set (low resistance) and reset (high resistance) states of Ta2O5/TiO2 resistive random access memory (ReRAM) was investigated to achieve low-voltage and multilevel operation. Since resistance in a set state tended to decrease due to the history effect of the lowest resistance, multilevel operation with a controlled set resistance was found to be difficult to achieve. On the other hand, the reset resistance could be controlled accurately by varying the reset voltage. The switching mechanism, the tunnel barrier of which is regenerated to cut off the filament, obtains the high repeatability of the reset resistance. As a result, a four-level storage ReRAM was successfully demonstrated with multireset level operation. In addition, the set voltage was found to strongly depend on reset resistance. Preventing reset resistance from exceeding 1 G¿ achieved a low-set-voltage operation below 5 V.

\hbox{Ta}_{2} \hbox{O}_{5}/\hbox{TiO}_{2}

This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A V/sub dd//2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.

Stack ReRAM for Low-Voltage and Multilevel Operation

A polymer solid-electrolyte (PSE) switch has been embedded in a 90-nm-node CMOS featuring a forming-less programming and extremely high on/off ratio of 105. A fast programming of 10 ns is also demonstrated for 50-nmΦ 1 k-b array by introducing the PSE switches integrated with a fully logic compatible process below 350°C. A high free volume in the PSE is supposed to result in the smooth formation of the Cu bridge without destroying the electrolyte, thereby also resulting in forming-less programming and high breakdown voltage. High disturbance reliability (T50; 50% fail) is extracted to be over 10 years at operation condition. The improved switching characteristics enable us to accurately program the crossbar circuit in a practical scale (32 × 32) without cell transistors. The developed switch is a strong candidate for realizing a low-power and low-cost nonvolatile programmable logic.

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

We have investigated off-state and turn-on characteristics of a Ta2O5-based solid-electrolyte switch, the resistance of which changes when the metallic current path is formed in the solid-electrolyte. The turn-on voltages are found to vary widely even when the switches are in an off-state with similar resistance. The variation is induced by the residual metal with different shapes that remains in the solid-electrolyte after a switch is turned off. The residual metal with a sharp point enhances the electrochemical reaction, resulting in the turn-on voltage lowering. We also developed a screening scheme to reduce the variation of the turn-on voltages.

Polymer Solid-Electrolyte Switch Embedded on CMOS for Nonvolatile Crossbar Switch

A 512kb MRAM comprising cross-point cells, magnetic tunnel junctions, bit lines and word lines is designed using a 0.25/spl mu/m CMOS and a 0.6/spl mu/m MRAM process. The design provides a new sensing method without a large area overhead despite a low current cross-point signal. The MRAM operates with read access time of 1.0/spl mu/s at 2.5V.

Off-state and turn-on characteristics of solid electrolyte switch

A capacitor-on-metal/via-stacked-plug (CMVP) memory cell was developed for 0.25 /spl mu/m CMOS logic embedded FeRAM. Using 445/spl deg/C MOCVD Pb(Zr,Ti)O/sub 3/ process, a ferroelectric capacitor is formed after CMOS logic fabrication. Thus, FeRAM can be embedded without changing any logic devices and processes. Furthermore, this technology enables cell size reduction (3.2 /spl mu/m/sup 2/ for 1T1C), minimum process damage on ferroelectric, and low manufacturing cost.

A 512kb cross-point cell MRAM

Programmable devices such as SRAM-based FPGAs have the major challenges of power consumption and circuit area due to the excessive standby leakage current and the threshold voltage variation in highly scaled SRAM. Back-end-of-line (BEOL) device, which is integrated in the interconnect layers, is attractive for reducing the performance gap between FPGA and cell-based ASIC [1–4]. In this paper, we demonstrate the fundamental operations of a programmable cell array and a 32×32 crossbar switch using a nonvolatile and rewritable solid-electrolyte switch (nanobridge or NB). A 72% reduction in chip-area compared with that of a standard-cell-based design is achieved on a 90nm CMOS platform.