Naoki Kasai

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

This paper presents a new nonvolatile magnetic flip-flop (MFF) for standby-power-critical applications. An MFF primitive cell for design libraries has been developed using 150 nm, 1.5 V CMOS and 240 nm MRAM processes. It has advantages over other nonvolatile flip-flops in high-speed store operations without endurance limitations. It also has high design compatibility with conventional CMOS LSI designs because it does not include any additional power lines and special transistors. A toggle frequency of 3.5 GHz was achieved by a SPICE simulation, which is comparable to that of a normal CMOS DFF in the same generation. The maximum frequency in a store operation was also estimated to be 500 MHz with 1-ns current width for the data backup. An MFF test chip, which includes 16-stage 8-bit shift register using MFFs, was fabricated with these processes. A 333 MHz store operation was measured without failed bits. The functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of systems on chips (SoCs) dramatically.

A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs

A novel capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) poly-Si storage node has been developed. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufacturable by optical delineation. The feasibility of the COB cell for 64-Mb DRAMs has been verified by a 64-kb test memory with 1.8- mu m/sup 2/ cells using a 0.4- mu m design rule, storage capacitance of 30 fF, 7-nm-SiO/sub 2/-equivalent dielectric film, and a storage node height of 0.5 mu m.<<ETX>>

A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 mu m/sup 2/. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm/sup 2/. >

Facet Formation in Selective Silicon Epitaxial Growth

Facets observed adjacent to insulator films in selective silicon epitaxial growth were studied. The facet formation depended on the crystallographic orientation of the openings, and facets did not appear adjacent to the SiO2 sidewall parallel to the [100] direction. Facet formation could also be suppressed by using a polysilicon-coated sidewall. Defects in the selective epi-layers were examined using transmission electron microscopy, and facet-free and defect-free epilayers were obtained.

Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs

This paper presents a new nonvolatile magnetic flip-flop (MFF) for standby-power-critical applications. An MFF primitive cell for design libraries has been developed using 150 nm, 1.5 V CMOS and 240 nm MRAM processes. It has advantages over other nonvolatile flip-flops in high-speed store operations without endurance limitations. It also has high design compatibility with conventional CMOS LSI designs because it does not include any additional power lines and special transistors. A toggle frequency of 3.5 GHz was achieved by a SPICE simulation, which is comparable to that of a normal CMOS DFF in the same generation. The maximum frequency in a store operation was also estimated to be 500 MHz with 1-ns current width for the data backup. An MFF test chip, which includes 16-stage 8-bit shift register using MFFs, was fabricated with these processes. A 333 MHz store operation was measured without failed bits. The functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of systems on chips (SoCs) dramatically.

Selective silicon epitaxial growth for device-isolation

Abstract Selective silicon epitaxial growth using the SiH 2 Cl 2 / HCl / H 2 system under reduced pressure was accomplished in windows surrounded by a fine patterned insulator film on a silicon substrate. Selectivity, surface planarity, and facet formation were studied as a function of growth pressure, growth temperature, and HCl flow rate during selective epitaxial growth. Defects, which were mostly pairs of stacking faults, were observed along sidewalls. The defect density in the epi-layer decreased with both decreasing growth temperature and increasing HCl flow rate. Electrical properties of p-n junctions fabricated in the epi-layers were investigated. Polysilicon gate MOSFETs were successfully fabricated on the epitaxial silicon layers. It was revealed that the selective epitaxial growth isolation was effective to reduce latch-up susceptibility for CMOS circuits. It has been discovered that the selective epitaxial growth is applicable to fine and deep isolation and can realize submicron geometry isolation for VLSI.

An effective channel length determination method for LDD MOSFETs

We propose a definition of MOSFET effective channel length (L/sub EFF/), that provides a method of determining L/sub EFF/ as a constant, and external resistance (R/sub EXT/) virtually as a constant, even for lightly doped drain (LDD) transistors. A unified relationship between this L/sub EFF/ and MOSFET drive current (linear and saturation) that is common to a wide range of drain structures was confirmed. Therefore, the L/sub EFF/ is useful, not only for compact analytical models, but also as an index of MOSFET performance applicable to both single drain and LDD devices. The dependence of the channel length on the source/drain structure was clarified by introducing the concept of local contribution to channel length. The L/sub EFF/ varies, even if the metallurgical channel length is fixed, depending on the design of the source/drain.

Evaluation of transistor property variations within chips on 300-mm wafers using a new MOSFET array test structure

A new test structure has been designed to evaluate fluctuations of transistor properties, both within a chip and across a 300-mm wafer. The evaluation system was established with a conventional parametric tester and dc power supplies suitable for application on production lines. It was observed that threshold voltage (V/sub th/) variations increased with the reduction of the channel area. A difference was also observed in the standard deviation (/spl sigma//sub vt/) between NMOS and PMOS. From statistical evaluations, controlling CDs and improving rolloff characteristics were found to be important to reduce V/sub th/ variations.

A 4-level storage 4 Gb DRAM

Bit-cost reduction is one of the most serious issues for file application DRAMs. Chip size reduction or density increase has been an effective solution. Lithographic technology has permitted this density increase through 70% reduction in the minimum design rule for each subsequent DRAM generation. However, for further density increase, another memory cell reduction technology is needed. Multi-level storage is one circuit technology that can reduce the effective cell size since it allows the storage of multiple voltage levels in a single memory cell functioning as a multi-bit memory. When four levels are stored in a single memory cell, the effective cell size is halved. The authors show that a charge-coupling sense amplifier, charge-sharing restore, and time-shared sensing increase speed and reduce sense-circuit area for 4 Gb DRAM.