Yukihide Tsuji

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

Recently there has been increased demand for not only ultra-low power, but also high performance, even in standby-power-critical applications. Sensor nodes, for example, need a microcontroller unit (MCU) that has the ability to process signals and compress data immediately. A previously reported 130nm CMOS and FeRAM-based MCU features zero-standby power and fast wakeup operation by incorporating FeRAM devices into logic circuits [1]. The 8MHz speed, however, was not sufficiently high to meet application requirements, and the FeRAM process also has drawbacks: low compatibility with standard CMOS, and write endurance limitations. A spintronics-based nonvolatile integrated circuit is a promising option to achieve zero standby power and high-speed operation, along with compatibility with CMOS processes. In this work, we demonstrate a fully nonvolatile 16b MCU using 90nm standard CMOS and three-terminal SpinRAM technology. It achieves 20MHz, 145μW/MHz operation with a 1V supply in the active state, and 4.5μW intermittent operation with 120ns wakeup time and 0.1% active ratio, without forwarding of re-boot code from memory. The features provide sufficiently long battery life to achieve maintenance-free sensor nodes.

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating

Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming the serious power-consumption problem that has rapidly become a dominant constraint on the performance improvement of todays VLSI processors. Normally-off and instant-on capabilities with a small area penalty due to non-volatility and three-dimensional-stackability of MTJ devices in the above structure allow us to apply a power-gating technique in a fine temporal granularity, which can perfectly eliminate wasted power dissipation due to leakage current. The impact of embedding nonvolatile memory devices into a logic circuit was, however, demonstrated by using only small fabricated primitive logic-circuit elements [3], memory-like structures such as FPGA [4], or circuit simulation because of the lack of an established MTJ-oriented design flow reflecting the chip-fabrication environment, while larger-capacity and/or high-speed-access MRAM has been increasingly developed. In this paper, we present an MTJ/MOS-hybrid video coding hardware that uses a cycle-based power-gating technique for a practical-scale MTJ-based NV-LIM LSI, which is fully designed using the established semi-automated MTJ-oriented design flow.

High-speed simulator including accurate MTJ models for spintronics integrated circuit design

An extremely practical simulation program with integrated circuits emphasis (SPICE) incorporating model parameters of magnetic tunnel junction (MTJ) was developed. The simulator provides reliable simulation results in spintronics circuit design because it can accurately calculate various MTJ characteristics that actual devices have, that considerably influence the operation margin and power dissipation. It can also accelerate the simulation speed, which makes it possible to simulate three times or more large-scale circuits than when a conventional macro-model is used.

Off-state and turn-on characteristics of solid electrolyte switch

We have investigated off-state and turn-on characteristics of a Ta2O5-based solid-electrolyte switch, the resistance of which changes when the metallic current path is formed in the solid-electrolyte. The turn-on voltages are found to vary widely even when the switches are in an off-state with similar resistance. The variation is induced by the residual metal with different shapes that remains in the solid-electrolyte after a switch is turned off. The residual metal with a sharp point enhances the electrochemical reaction, resulting in the turn-on voltage lowering. We also developed a screening scheme to reduce the variation of the turn-on voltages.

Low temperature process for CMUT fabrication with wafer bonding technique

We present the successful fabrication of capacitive micromachined ultrasonic transducers (CMUTs) based on low temperature wafer bonding (< 400°C). Such a fabrication process enables the direct integration of CMUTs on top of IC substrates, and requires only two additional lithography steps for fabricating the complete CMUT. Our approach benefits from both the integrated electronics and the well-controlled performance of CMUTs with single-crystal silicon plates. The yield of the CMUTs is almost 100%, and the standard deviation of resonance frequency in air is less than 1% in the whole 4 inch wafer.

Highly scalable nonvolatile TiOx/TaSiOy solid-electrolyte crossbar switch integrated in local interconnect for low power reconfigurable logic

A fully logic-compatible, nonvolatile crossbar switch using a novel dual-layer TiOx/TaSiOy solid-electrolyte, “NanoBridge”, has been developed for the first time, which is scalable to 50 nm and beyond and keeps the extremely low ON-resistance of ≪100 Ω. A key breakthrough is the dual-layer solid-electrolyte, in which TiOx works as an oxygen absorber as well as a superior ionic conductor, thus improving the yield, ON/OFF resistance ratio (≫106) and cycling endurance (≫103). The highly scalable 4 × 4 crossbar switch composed of NanoBridge integrated in a local Cu interconnect of a standard CMOS is successfully configured without select transistors. The nonvolatile solid-electrolyte, crossbar switch is a promising switch element for low power and low cost reconfigurable logic.

High-speed and reliable domain wall motion device: Material design for embedded memory and logic application

High-speed capability and excellent reliability of a magnetic domain wall (DW) motion device required for embedded memory and logic-in-memory applications were achieved by optimizing the film stack structure of Co/Ni wire. Low-current with high-speed writing, high heat resistance, low error rate, wide operation range for temperature and magnetic field, high retention, and high endurance features were confirmed.

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction

A magnetic tunnel junction (MTJ)-based logic-in-memory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ device model produced by the fabricated test chips. Through the measurement results of the fabricated LSI, this study shows both the impact of the power-gating technique in a fine temporal granularity utilizing the non-volatility of the MTJ device and the effectiveness of the established automated design environment for designing random logic LSI using nonvolatile logic-in-memory.

A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPUs internal state, this MPU realizes power-gating operation with a small 3-microsecond entry/exit delay penalty in power-on/power-off, which is one order of magnitude faster than a conventional MPUs deep power down mode. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems because of its easy controllability for the power gating mode.

Spintronics primitive gate with high error correction efficiency 6(P error ) 2 for logic-in memory architecture

A spintronics primitive gate with redundancy was designed using domain wall motion (DWM) cells, and the data-missing rate was drastically improved to ~6 (Perror)2 when the error rate per DWM cell was Perror. All the DWM cells aligned in series were written simultaneously, which suppressed the increase in power consumption when writing. Application of 4-terminal DWM cells with physically separated current paths for writing and reading saved extra path transistors for redundancy and there were no area overheads.