Hiroo Hongo

Ultrafine Fabrication Technique for Hot Electron Interference/Diffraction Devices

We proposed a device for observing hot electron interference by a double slit. For this purpose we had refined and improved the fabrication techniques, especially electron beam lithography; the alignment of electron beam lithography before and after crystal growth with accuracy of 100nm was reported for the first time. We could form detection electrodes of fine pitch on a narrow mesa structure. The formation of a 50-nm-pitch InP buried structure was also reported.

A 40-nm-pitch double-slit experiment of hot electrons in a semiconductor under a magnetic field

We report a double-slit experiment of hot electrons in a semiconductor under a magnetic field. The pitch of the double slit buried in the semiconductor is 40 nm and the electron energy is of the order of 100 meV. By applying a magnetic field, the change in current that passes through the slits is observed at the segmented collector. The measured current shows a clear minimum around B=0 T, with this behavior agreeing with a theoretical calculation based on double-slit interference. Quantitative estimation is consistent with this order of current variation. We think that these results show evidence of the observation of hot electron interference by a double slit in a semiconductor.

Nanostructure Alignment for Hot Electron Interference/Diffraction Devices

An ultrafine fabrication technique for hot electron interference/diffraction devices was developed. The alignment of two nanostructures by e-beam direct writing before and after crystal growth was reported for the first time. The aligned structure consists of 70 nm pitch grating GaInAs/InP buried structure and 70 nm pitch stripe electrode of Cr/Au.

Influence of a finite energy width on the hot electron double-slit interference experiment: A design of the emitter structure

The influence of electron energy width in the hot electron double-slit experiment is investigated quantitatively. The required condition on the Fermi level in the emitter and the slit-spacing is derived for the experiment. In order to achieve a coherent electron source, a single-barrier graded emitter structure is discussed and its characteristics are considered. For application to the hot electron double-slit experiment, the graded emitter diode is fabricated and the current–voltage relation is measured in a supplementary experiment.

Resolution of 1:1 Electron Stepper with Patterned Cold Cathode

We investigated the feasibility of 1:1 electron stepper lithography based on a patterned cold cathode. We fabricated metal-semiconductor-insulator cold cathodes and measured the energy distribution of the emitted electrons. Based on the finite width of the energy distribution, we simulated the emission of the electron beam from one point on the cold cathode broadens at the wafer surface by solving the equation of motion. The simulation showed that when the energy width was 360 meV, the beam spread was estimated to be approximately 23 nm. This indicates that if we fabricate a 20-nm-wide emission area, the electron beam width on the wafer could be approximately 43 nm. Therefore, we conclude that the 1:1 electron stepper can achieve a 50-nm resolution.

WRAPPED ALIGNMENT MARKS FOR FABRICATION OF INTERFERENCE/DIFFRACTION HOT ELECTRON DEVICES

A wrapped alignment mark structure is proposed for a nano-fabrication process by e-beam lithography (EBL) with organometallic vapor phase epitaxy regrowth. To protect the alignment marks during regrowth, a SiO2 layer covers the surface of the gold mark and a thin tungsten layer is inserted between the mark and the substrate. The waveform serving as a mark detection signal is not significantly reduced after regrowth. By employing this mark system in EBL, an aligned nanostructure with a buried double-slit heterostructure and fine multi-electrodes is fabricated successfully to show the feasibility of this alignment mark method of wrapping. The center to center spacings of the double-slit and the fine electrodes are 40 nm and 50 nm, respectively.

Seventy-nm-Pitch Patterning on CaF 2 by e-beam Exposure

We report fine pitch patterns of polycrystalline \caf film deposited on an InP substrate formed by e-beam exposure. Ten periods of 70-nm-pitch line patterns were fabricated. The linewidth fluctuation was found to depend on the grain size of the \caf film.

Top-Gate Carbon-Nanotube Field-Effect Transistors with Very High Intrinsic Transconductance

1Fundamental Research Laboratories, NEC Corporation, Tsukuba 305-8501, Japan Phone:+81-29-850-1584 Fax: +81-29-856-6139 E-mail: nihey@frl.cl.nec.co.jp 2Japan Science and Technology Corporation, c /o NEC Corporation, Tsukuba 305-8501, Japan 3Japan Fine Ceramics Center, c /o National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba 305-8565, Japan 4Research Center for Advanced Carbon Materials, AIST, Tsukuba 305-8565, Japan 5Faculty of Science and Technology, Meijo University, Tenpaku-ku, Nagoya 468-8502, Japan

A 25-nm-pitch GaInAs/InP Buried Structure Using Calixarene Resist.

To realize a fine periodical pattern by electron beam lithography, a stady for using calixarene as a resist was carried out. A 25-nm-pitch resist pattern was fabricated and transferred to a thin InP layer by two-step wet chemical etching. Precise slight O2 ashing, to eliminate residual matter was essential to transfer the pattern by wet etching. The controllability of the width was improved when using calixarene, when the period was 40 nm. Furthermore, a 25-nm-pitch InP pattern was buried in a GaInAs structure by organometallic vapor phase epitaxy. This technology could be applied to realize electron wave devices.

Hot electron interference by 40 nm-pitch double slit buried in semiconductor

Abstract We report a double-slit experiment of hot electrons in semiconductor under a magnetic field. The pitch of the double slit buried in the semiconductor is 40 nm, and the electron energy is in the order of 100 meV. By applying a magnetic field, the change in current which passes through the slits is observed at the segmented collector. The measured current shows a minimum around B = 0 T. A simulation is presented which is based on the Fraunhofer diffraction and the path integral method. The simulation predicts the variation of current, and quantitative estimation is consistent with the order of measured current variation. We think that these results imply the hot electron interference by a double slit in a semiconductor.