Michihiko Suhara

Lateral confinement in a resonant tunneling transistor with a buried metallic gate

We have fabricated a resonant tunneling transistor by epitaxial overgrowth over a tungsten grating placed 30 nm above a GaAs/GaInP semiconductor, double barrier, resonant tunneling heterostructure. The Schottky depletion around the buried metal contacts controls the current to a vertical transistor channel. The lateral extension of this channel is defined by a square opening in the grating with a side length of 1.4 μm, which corresponds to a sub-μm electrical width. The transport properties at 20 K show a fine structure in the resonant tunneling characteristics, and it is affected by the gate bias. These effects are discussed in terms of lateral quantum confinement in the transistor channel defined.

Proposal of buried metal heterojunction bipolar transistor and fabrication of HBT with buried tungsten

We propose a buried metal heterojunction bipolar transistor (BM-HBT), in which buried metal in the collector layer could reduce the total base-collector capacitance. To show the possibility of making a BM-HBT, we fabricated an InP-based HBT with buried tungsten mesh replacing the subcollector layer, where tungsten mesh works as a Schottky collector electrode. A flat heterostructure on the InP collector layer of the buried tungsten mesh was confirmed by a cross-sectional SEM view. A DC current gain of 12 was measured from the common-emitter collector I-V characteristics.

A 40-nm-pitch double-slit experiment of hot electrons in a semiconductor under a magnetic field

We report a double-slit experiment of hot electrons in a semiconductor under a magnetic field. The pitch of the double slit buried in the semiconductor is 40 nm and the electron energy is of the order of 100 meV. By applying a magnetic field, the change in current that passes through the slits is observed at the segmented collector. The measured current shows a clear minimum around B=0 T, with this behavior agreeing with a theoretical calculation based on double-slit interference. Quantitative estimation is consistent with this order of current variation. We think that these results show evidence of the observation of hot electron interference by a double slit in a semiconductor.

Characterization of GaInAs/InP triple-barrier resonant tunneling diodes grown by organo-metallic vapor phase epitaxy for high-temperature estimation of phase coherent length of electrons

To estimate the phase coherent length(L C) of electrons in semiconductor, triple-barrier resonant tunneling diodes (TBRTDs) with GaInAs/InP heterostructures were fabricated by using organo-metallic vapor phase epitaxy (OMVPE). The current density-voltage (J-V) characteristics were measured at 4.2 K and 77 K. Moreover method of comparison between experimental and theoretical results is proposed. By comparing experimental result with theoretical result, the coherent lengths are estimated to be longer than 90 nm and 55 nm at 4.2 K and 77 K respectively.

EFFECT OF SPACER LAYER THICKNESS ON ENERGY LEVEL WIDTH NARROWING IN GAINAS/INP RESONANT TUNNELING DIODES GROWN BY ORGANO-METALLIC VAPOR PHASE EPITAXY

We studied the effect of spacer layer thickness on the resonant level width in resonant tunneling diodes (RTDs). GaInAs/InP RTDs were fabricated with various spacer layer thicknesses using organo-metallic vapor phase epitaxy, and the resonant level width was estimated. As a result, the resonant level width was found to decrease with increasing spacer layer thickness. To discuss this tendency, a theoretical model of the interface fluctuation between spacer layers and electrodes, caused by the random distribution of the impurity ions in electrodes, was proposed.

Lateral current confinement in selectively grown resonant tunneling transistor with an embedded gate

We report on fabrication and measurements of a selectively grown vertical resonant tunneling transistor with lateral current constriction. A GaInP/GaAs/GaInP, 3/9/3 nm, double barrier structure is epitaxially grown over a grating of tungsten (W) wires, where the Schottky depletion around the embedded wires creates a semi-insulating layer. The vertical current in the device passes the semi-insulating region through a designed opening (1×1μm2) in the grating, which, taking the depletion region into account, gives a transistor with an electrical area of well below 1μm2. Current–voltage (I–V) measurements at 4 K show a multitude of current peaks that respond strongly to the gate voltage applied to the metal grating. From the gate response and the small lateral area, we believe that these peaks arise from lateral confinement effects.

Peak Width Analysis of Current–Voltage Characteristics of Triple-Barrier Resonant Tunneling Diodes

We studied the peak width of current vs voltage (I–V) characteristics of triple-barrier resonant tunneling diodes (TBRTDs) experimentally and theoretically. A GaInAs/InP TBRTD was fabricated by organo metallic vapor phase epitaxy (OMVPE). A theory of I–V characteristics of TBRTDs was developed by taking the structural inhomogeneity into account to explain the experimental peak width. The fluctuation of the well width in a TBRTD grown by OMVPE was estimated as two atomic layers.

Toward nano-metal buried structure in InP – 20 nm wire and InP buried growth of tungsten

Abstract Toward nano-metal buried structure in InP, we studied the fabrication process of nano-tungsten wire and the InP buried growth of tungsten stripes. A tungsten wire with a 20 nm width was fabricated by the proposed metal-stencil liftoff, in which gold/chromium and SiO 2 replace resist to prevent thermal deformation in a conventional liftoff process. The buried growth of tungsten stripes with 1 μ m widths and 2 μ m pitch by organometallic vapor phase epitaxy (OMVPE) was studied. Tungsten stripes were buried under the flat InP layer of 1.1 μ m thickness, and the ratio of grown InP thickness to buried tungsten width was about 1.

High Peak-to-Valley Current Ratio GaInAs/GaInP Resonant Tunneling Diodes

As an Al-free material system, the GaInAs/GaInP heterostructure has a large conduction-band discontinuity. We report the fabrication of GaInAs/GaInP resonant tunneling diodes which exhibit current density-voltage characteristics with a peak-to-valley current ratio of 7.8 at 4.2 K. To our knowledge, this is the highest value obtained for this material system.

WRAPPED ALIGNMENT MARKS FOR FABRICATION OF INTERFERENCE/DIFFRACTION HOT ELECTRON DEVICES

A wrapped alignment mark structure is proposed for a nano-fabrication process by e-beam lithography (EBL) with organometallic vapor phase epitaxy regrowth. To protect the alignment marks during regrowth, a SiO2 layer covers the surface of the gold mark and a thin tungsten layer is inserted between the mark and the substrate. The waveform serving as a mark detection signal is not significantly reduced after regrowth. By employing this mark system in EBL, an aligned nanostructure with a buried double-slit heterostructure and fine multi-electrodes is fabricated successfully to show the feasibility of this alignment mark method of wrapping. The center to center spacings of the double-slit and the fine electrodes are 40 nm and 50 nm, respectively.