Hiroomi Nakao

A flexible multiport RAM compiler for data path

A multiport RAM compiler with flexible layout and port organization has been developed using 1.0- mu m CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. The targeted feature is the flexibility in both layout and port organization. Fast access time and fully static and asynchronous port operation are also goals. A wide bit-word organization range including 16 b*2048 words and 72 b*512 words was also obtained. This compiler generates up to 32 K three-port RAM and 16 K six-port RAM. In addition to READ and WRITE ports, READ/WRITE ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no DC power consumption. The address access times of the generated three-port RAMs are, for example, 5.0 ns for 1 K and 11.0 ns for 32 K. >

A new hierarchical algorithm for transistor placement in CMOS macro cell design

We present a new transistor placement algorithm for generating a uni-height macro cell layout. The algorithm first partitions the transistors constituting a cell into clusters, and provides a set of alternative transistor placements in a cluster for each cluster. And then both selection from each set and placement of clusters are performed simultaneously, by iterative improvement method. This simultaneous improvement method enables one to get a good solution in practical time. Experimental results on our gate-array cell library shows that the resultant placements are comparable to manual placements done by skilled layout designers, in terms of width and intra-cell routing congestion.

A CMOS cell generation system for two-dimensional transistor placement

This paper presents an automatic layout generation system for CMOS uniform height cells with a two-dimensional layout style. The two-dimensional layout style described in this paper is effective with such cells as consist of considerably varied sizes of transistors. The proposed system generates a high density layout of such cells. To show the effectiveness of the two-dimensional layout style, we compared cell layouts generated by the proposed system with cell layouts in the traditional one-dimensional layout style, for various cell heights. Moreover, the experimental results show that the generated layouts are comparable in terms of cell area to manual two-dimensional layouts done by skilled layout designers.

A Fast Eliminating System of Narrow Electron-Beam Exposure-Figures for Improving Pattern Accuracy

We have developed a system for fast elimination of narrow electron-beam (EB) exposure-figures, which degrade pattern accuracy when using a variable shaped writing scheme. In order to reduce the processing time, a hierarchical and a distributed processing method have been developed. In addition, two kinds of narrow-figure elimination methods have been evaluated for further reduction of the processing time: a whole figure-merge method and a pinpoint figure-merge method. It was found that both methods must be selectively used because the best method strongly depends on the total amount of initial narrow figures in input data. The developed system has been applied to EB exposure data for 5× reticles of a 256 Mbit dynamic random access memory (DRAM). The pinpoint figure-merge method was used because its processing speed was 1.5 times higher than the other method for this case. The narrow-figure elimination has been completed successfully in a practical time; it was 2.8 hours for 4 critical layers of a 256 Mbit DRAM.