Masayuki Terai

A new min-cut placement algorithm for timing assurance layout design meeting net length constraint

This paper presents a new min-cut placement algorithm for timing assurance layout design. When critical nets are given net length constraints, the proposed algorithm can place cells so that the constraints may be met. This algorithm is built into the layout system for gate arrays called GALOP [1] and has been successfully applied to clock skew control of an ECL 12K-gate gate array.

Physical Model for Reset State of Ta2O5/TiO2-Stacked Resistance Random Access Memory

We investigated the conduction mechanism of a Ta2O5/TiO2-stacked resistance random access memory (ReRAM) device and found that its highly resistive state can be attributed to tunnel barriers induced in the filament, since single-electron tunneling phenomena was observed in the current–voltage characteristics at low temperatures and the resistance depended only slightly on temperature. We also found that the largest tunnel barrier, whose resistance is more than 1000 times larger than the second largest one, is located at the interface between the Ta2O5 layer and TiO2 layer and that variation in the resistance was caused by variation in the tunnel barrier width.

1.2 nm HfSiON/SiON stacked gate insulators for 65-nm-node MISFETs

We have investigated a Hf-based CMOSFET fabrication method that would enable the high performance and low gate leakage current that are required for the 65-nm-node CMOS devices. To suppress the gate leakage in a gate stack with an equivalent oxide thickness (EOT) of 1.2 nm, the upper layer of HfSiO film was thickened and nitrided. The nitridation improves the dielectric constant, allowing the use of a thicker HfSiO layer. The mobility was improved by lightly nitriding the bottom SiO2 interface layer, which suppresses the interfacial trap generation. Such techniques enabled us to achieve a good EOT vs Ig relationships. The Ig at an EOT of 1.2 nm was reduced by three orders of magnitude as compared with that with a SiO2 gate insulator. High mobilities, 87% of that of a SiO2 MOSFET for an NFET and 96% for a PFET, were also obtained.

Min-cut placement with global objective functions for large scale sea-of-gates arrays

We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms were developed based on a single local optimization function, called the sequential cut line objective function. Our algorithm incorporates global objective functions into this traditional framework of min-cut placement. In particular, we introduce a new global objective function based on the congestions for cut lines and use it for the selection of their sequence. We also use the total cut value objective function in the determination of the sizes and connectivities of clusters that are to be used in the early stages of min-cut partitioning. The incorporation of such global objective functions yields additional reductions of wire congestions in the entire as well as local chip areas. With the automatic selection and use of such clusters and a cut line sequence, our algorithm can produce, in a short time and at a low cost, final placement results that achieve the 100% completion of wiring on chips of fixed sizes. This has led to its successful production use, having generated more than 400 CMOS sea-of-gates array chips of 1.5 K to 150 K raw gates. >

A new model for over-the-cell channel routing with three layers

The authors propose an approach to an over-the-cell channel routing problem using a model that consists of two channels and the routing area over a cell row between them. Three and two layers are available for routing in the channels and the over-the-cell routing area, respectively, The problem is decomposed into two phases: over-the-cell routing and channel routing. The authors formulate the problem in the first phase as that of channel routing with additional constraints. Based on this formulation, they present an efficient over-the-cell routing algorithm. The effectiveness of the approach is demonstrated by experimental results on sea-of-gates array chips.<<ETX>>

Influence of Charge Traps within HfSiON Bulk on Positive and Negative Bias Temperature Instability of HfSiON Gate Stacks

We characterized how positive and negative bias temperature instabilities (PBTI and NBTI) occur in HfSiON gate stacks. The PBTI was confirmed to be suppressed by using amorphous (a-) HfSiON instead of crystallized (c-) HfSiON. The a-HfSiON reduced the capture cross-section and lowered the density of electron traps, which explains the suppression of the PBTI. The different trap parameters for a-HfSiON and c-HfSiON suggest that the electron traps of these structures have different origins. The PBTI of a-HfSiON gates occurred through electron trapping without generation of interface traps, while the NBTI of a-HfSiON gates occurred through generation of interface traps and positive oxide charges. Furthermore, it was found that the NBTI of a-HfSiON gates also involves electron trapping. Additionally, the subthreshold slope decreased under positive BT stress. We attribute these characteristic BTI behaviors of HfSiON gates to the influence of charge traps that are present within the HfSiON bulk.

A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays

The channel router, which routes a rectangular channel with two rows of terminals along its top and bottom sides, is extensively used for the automatic routing of gate arrays. It is well known that in this routing method the routing can not be performed when the vertical constraint graph contains cycles. This paper deals with the problem of eliminating cycles in the vertical constraint graph by interchanging the nets assigned to logically equivalent terminals before channel routing. A heuristic algorithm is proposed for this problem. This algorithm yields a locally optimum assignment of nets to terminals, in the sense that the number of independent cycles in the vertical constraint graph of a resultant assignment can not be reduced by interchanging any pair of the nets assigned to logically equivalent terminals. Furthermore, in order to speed up the operation of this algorithm, it is shown that the checking as to whether or not the number of independent cycles in the vertical constraint graph is reduced can be done by noting only its subgraph, when a pair of nets assigned to logically equivalent terminals are interchanged. Experimental results have indicated that this proposed algorithm is efficient.

A congestion-driven placement improvement algorithm for large scale sea-of-gates arrays

A fast placement improvement algorithm for large scale gate arrays is reported. This algorithm consists of a new cell padding phase and a fast iterative improvement phase. To reduce local routing congestion on a chip, the padding phase virtually expands the size of cells in the congested regions and relocates all the cells to eliminate the cell overlap, preserving the relative cell position. We have developed a formula by which to estimate from the expanded cell sizes the congestion after the relocation in each region on a chip. Using this, the padding phase determines cell sizes that will equalize the congestion throughout a chip, by simulated annealing. The iterative improvement phase minimizes the well known objective function that takes the local congestion into account, but our algorithm is faster because of the use of a new gain estimation method for determining a better position to which to move a cell. The experimental results on large gate array designs indicate that the routability of cell placement is considerably improved by our algorithm.

Memory-State Dependence of Random Telegraph Noise of

Memory-state [low-resistance state (<i>R</i>_L) and high-resistance state (<i>R</i>_H)] dependence of random telegraph noise (RTN) of Ta₂O₅/TiO₂ resistive random access memory is investigated. The conduction mechanism of both memory states and a limit of resistance controllability are also investigated to clarify the difference in the RTN mechanism of both states. The boundary between the <i>R</i>_L and <i>R</i>_H states was found at 5-20 kΩ , and the conduction mechanism much depended on the memory state. The noise also depended on the memory state. The noise amplitude in the <i>R</i>_H state was larger than that in the <i>R</i>_L state. In the <i>R</i>_H state, a tunnel barrier was generated to cut off a conduction path (filament), and traps inside the tunnel barrier were supposed to increase the noise amplitude. Moreover, the composition of the following degraded the noise distribution in the <i>R</i>_H state: 1) capture and emission of charges with traps and 2) instability of these traps against the bias temperature stress.

\hbox{Ta}_{2}\hbox{O}_{5}/\hbox{TiO}_{2}

We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms used a fixed cut line sequence that is determined before min-cut partitioning is performed. In our approach, we adaptively select a next partitioning pattern based on the current parameter value; we then perform the corresponding min-cut partitionings and measure a new parameter value. We repeat this process until all cut lines are processed. As a parameter, we introduce a new global objective function based on wire congestions on cut lines. We establish a close relation between this function and cut line sequences. This relation is used to develop an innovative method of adaptively determining a cut line sequence so as to minimize this global function. With this adaptive selection of cut lines along with a new cluster-based min-cut partitioning technique, our algorithm can produce, in a short time and at a low cost, final placement results that achieve the 100% completion of wiring on chips of fixed sizes. This has led to its successful production use, having generated more than 400 CMOS sea-of-gates array chips.