Kaoru Okazaki

A Multiple Media Delay Simulator for MOS LSI Circuits

This paper concerns an accurate delay modeling of MOS gates at the logic level. The model takes account of the effects of not only the loading capacitance but also the slope of the input waveform. A logic simulator which uses multiple rise/fall delays based on the model is described. Some experimental results are also presented.

A High Density Data Path Generator With Stretchable Cells

This paper describes a newly developed module generator for data-path. Function blocks are designed in 0.8pm double metal CMOS technology. Adopting new cell structure for over the cell routing, called “stretchable cell with access free terminals (SCAT)”, high density of more than 7K trs./mm* and high performance data-path has been obtained. 1 Jntroduct ion Recently, it has become more important how to design customized data-paths in short time, since they are the key elements to attain high performance. Among them, data-paths of bit-parallel structure are often used in digital video and image processing LSls. To implement this type of data-path, it is more effective to take a module generation approach than to use conventional standard cells, because it is highly structured and has high regularity. In most data-path generators, the entire data-path layout is obtained by routing each function block(FB) mutually, which is a component of the datapath such as ALU or register file. Targeting high density data-path layout, over the cell routing method had been applied [l]. However, an extra off the cell routing region was inevitable, because wiring tracks which terminals of FBs could access were fixed. This paper describes a newly developed module generator for cell-based design which generates datapath layout comparable to handcrafted one both in speed and density. To eliminate the extra routing region, the most suitable cell structure for over the cell routing, the “stretchable cell with access free terminals (SCAT)”, has been developed. 11.3.1 IEEE 1992 CUSTOM INTEGRATED CIRCUITS CONFERENCE 2.Lavout structure Fig.1 shows a layout structure of generated 8 bit datapath. The features of generated data-path layout are as follows. 1)FBs are arranged horizontally, abutting on each other. 2)Each FB consists of two parts, the control unit (such as address decoder or flag generating circuit) and the execution unit. 3)The execution unit has bit-slice like structure vertically. Within each bit-slice element a pair of power lines (VDD,VSS) run horizontally in second metal. 4)The control lines run vertically in first metal, and the data lines run horizontally in second metal. It is most notable that no extra wiring region between FBs for changing tracks exists in this structure, which provides higher density of the generated layout. This advantage is realized using SCAT as the bit-slice element(See Fig.2). Fig. 1 Layout Structure of Generated 8bit Data path 0-7803-0246-Xl92

An Integrated Computer Aided Design System for Gate Array Masterslices: Part 2 The Layout Design System Mars-M3

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A high density datapath layout generation method under path delay constraints

Described are the outline and the application results of a fully automatic chip layout design system which has been utilized for years for the development of over a hundred options of ECL and MOS gate arrays. The features and techniques of the placement, routing and checking subsystems as well as the chip layout model which can be treated by the system are discussed.

A congestion-driven placement improvement algorithm for large scale sea-of-gates arrays

A novel method for producing high-density datapath layouts under path delay constraints is proposed. The authors have adopted an array-compiler for generating layouts of functional blocks, and a place-and-route program for generating an overall layout. For linear placement of functional blocks, they have applied the A-algorithm with a new cost function which has the terms of path delay constraints and track number. This makes it possible to find a placement of functional blocks which leads to a high-density datapath layout that satisfies all path delay constraints. With the proposed method, the authors successfully generated several datapath layouts realizing the desired performance. The density of the layout ranges from 6.1 to 8.5Ktr./mm/sup 2/, which is sufficiently high.

A CMOS cell generation system for two-dimensional transistor placement

A fast placement improvement algorithm for large scale gate arrays is reported. This algorithm consists of a new cell padding phase and a fast iterative improvement phase. To reduce local routing congestion on a chip, the padding phase virtually expands the size of cells in the congested regions and relocates all the cells to eliminate the cell overlap, preserving the relative cell position. We have developed a formula by which to estimate from the expanded cell sizes the congestion after the relocation in each region on a chip. Using this, the padding phase determines cell sizes that will equalize the congestion throughout a chip, by simulated annealing. The iterative improvement phase minimizes the well known objective function that takes the local congestion into account, but our algorithm is faster because of the use of a new gain estimation method for determining a better position to which to move a cell. The experimental results on large gate array designs indicate that the routability of cell placement is considerably improved by our algorithm.

A new router for reducing "antenna effect" in ASIC design

This paper presents an automatic layout generation system for CMOS uniform height cells with a two-dimensional layout style. The two-dimensional layout style described in this paper is effective with such cells as consist of considerably varied sizes of transistors. The proposed system generates a high density layout of such cells. To show the effectiveness of the two-dimensional layout style, we compared cell layouts generated by the proposed system with cell layouts in the traditional one-dimensional layout style, for various cell heights. Moreover, the experimental results show that the generated layouts are comparable in terms of cell area to manual two-dimensional layouts done by skilled layout designers.