Hiroshi Domyo

A manufacturable SOI CMOS process for low power digital, analog, and RF applications

Peregrine Semiconductors UTSi(R) technology is a silicon-on-sapphire (SOS) CMOS process with proven manufacturability for high-performance, low-power commercial CMOS applications. Data are presented from the 0.7/spl mu/m single poly, triple metal process currently in production. The UTSi(R) CMOS process is compatible with standard CMOS processing equipment and techniques. Process parameters show excellent control and the process has demonstrated high reliability. Transistor and device parametric performance show this process to be capable of manufacturing low power products for digital, RF, and analog applications. The technology is fully qualified in plastic packages and is ready for high volume, low cost production. The process is shown to be scaleable to at least 0.5/spl mu/m for further performance gains.

Monitoring the Electrical Properties of the Back Silicon Interface of Silicon-on-Sapphire Wafers

The density and the electrical nature of the interface traps at the silicon-sapphire interface of silicon-on-sapphire (SOS) MOSFETs have a significant influence on the electrical characteristics of these transistors. This letter describes a simple MOS test structure for evaluating the electrical properties of this interface of SOS wafers. Measurement and modeling of the C-V characteristics of the test structure fabricated on production SOS wafers are presented. We have demonstrated that the C-V characteristics are an efficient tool for studying the depletion of the silicon-sapphire interface by the interface trapped charge.

Improvement in off-State Leakage Current of n-Channel SOS MOSFETs by Hydrogen Annealing of the SOS Film

The off-state source-to-drain leakage current and punchthrough voltage are the quantities that frequently limit the performance of short-channel floating-body silicon-on-sapphire (SOS) n-channel MOSFETs. In this paper, we demonstrate that the high-temperature hydrogen annealing of the SOS film prior to the device fabrication leads to marked improvement in these two parameters. The effect is attributed to the impact of hydrogen on the out-diffused thin alumina layer formed at the silicon-sapphire interface during the anneal. The thin alumina layer acting as a p-type dopant source at the back interface eliminates the back surface depletion of SOS n-MOSFETs. It also acts as a recombination center to eliminate the floating-body effect of floating-body n-MOSFETs. This technique provides a practical and reliable process to build short-channel floating-body SOS n-MOSFETs with off-state leakage as low as the junction leakage and punchthrough voltage as high as 6 V or higher at the gate length of 0.5 μm without any degradation on the inversion layer carrier mobility or increase in the junction leakage current.

Comparison of the RF characteristics of inversion channel and depletion channel SOS MOSFETs

Measurement of small-signal equivalent circuit parameters was carried out to estimate the RF performance of conventional inversion channel and depletion channel SOS MOSFETs. It was shown that the latter has significantly higher cutoff frequency fT attributed to electron mobility of the depletion channel.

Extraction of RF equivalent circuit and semiconductor parameters of SOS MOSFETs from S-Parameter measurements

This paper describes the use of on-wafer measured microwave scattering parameters (S-parameters) for the extraction of RF equivalent circuit elements and semiconductor parameters of an SOS MOSFET.

Origin of the low frequency type curve in Silicon-on-Sapphire MOS capacitors

MOS capacitor C-V measurement is a standard tool for investigating the electrical properties of a wafer. This paper investigates the use of a novel MOS capacitor structure for use with thin film silicon-on-sapphire wafers in order to determine backs surface silicon-sapphire interface quality.