Y.T. Yeow

MOSFET degradation due to stressing of thin oxide

Oxide and interface traps in 100Å oxide created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at high fluence, becomes negative due to the trapping of electrons at 60Å from the injector (cathode) interface. Acceptor and donor type interface traps (surface states) peaking at 0.65eV above valence band edge were created by tunneling current from and to the substrate respectively. The interface traps cause degradations in subthreshold current slope and surface mobility. The threshold voltage shift can be either positive or negative under the combined influence of the oxide charge and the interface traps.

High quality ultrathin dielectric films grown on silicon in a nitric oxide ambient

High quality ultrathin silicon oxynitride films (3.5 nm) have been grown in a nitric oxide ambient using rapid thermal processing. The physical and electrical properties of these films are compared with those formed in a nitrous oxide environment. X‐ray photoelectron spectroscopy (XPS) results show that the nitric oxide (NO) grown films have a significantly different nitrogen distribution compared to the nitrious oxide (N2O) grown films. The capacitance‐voltage and current‐voltage characteristics of the NO grown and NO‐modified films are, in general, better than those of the same thickness grown in either N2O or O2.

Effects of nitric oxide annealing of thermally grown silicon dioxide characteristics

The effects of nitric oxide (NO) annealing on conventional thermal oxides are reported in this letter. The oxide thickness increase, resulting from NO annealing, is found to be only a few angstroms (<0.5 nm) and independent on the initial oxide thickness. Furthermore, both the electrical and physical characteristics are improved. This technique is expected to achieve sub-5 nm high quality ultrathin dielectric films for the applications in EEPROMs and ULSI.<<ETX>>

Observation of MOSFET degradation due to electrical stressing through gate-to-source and gate-to-drain capacitance measurement

The authors present observations of changes in the gate capacitances of a MOSFET as a result of hot-carrier stressing and propose capacitance measurement as a method for evaluation of trapped charge. The effect of hot-carrier stressing on 2- mu m effective channel length n-channel MOSFETs was monitored by measuring the gate-to-source capacitance and the gate-to drain capacitance. It was found that after electrically stressing a junction of the transistor, capacitances associated with the stressed junction were reduced, whereas the capacitances of the unstressed junction were found to have increased. The observation is explained in terms of the change in channel potential near the stressed junction due to negative trapped charge.<<ETX>>

The electrical properties of sub-5-nm oxynitride dielectrics prepared in a nitric oxide ambient using rapid thermal processing

Ultrathin (<5 nm) dielectric films have been grown on <100> silicon using rapid thermal processing (RTP) in a nitric oxide (NO) ambient. Interface state density, charge trapping properties, and interface state generation during Fowler-Nordheim electron injection have been investigated. The films grown in NO have excellent electrical properties. These properties are explained in terms of a much stronger and large number of Si-N bonds in both the bulk of the dielectric films and at the Si-SiO/sub 2/ interface region. The leakage currents are at least three orders of magnitude lower than other reported results for similar thicknesses. The dielectric films grown in NO ambient are viewed as promising technology for ultrathin dielectrics.<<ETX>>

Creation and termination of substrate deep depletion in thin oxide MOS Capacitors by charge tunneling

Deep depletion in both p-type and n-type substrates can be induced by minority carriers tunneling away from the substrate. When this occurs, tunneling current becomes saturated at the rate of carrier generation in the substrate, with the excess applied voltage dropped across the deep-depletion region. We present a quantitative model for this phenomenon based on balancing the tunneling current and the space-charge generation current. Conversely, the usual transient deep depletion in n-type substrate MOS capacitors can be terminated by tunneling-induced electron-hole pair generation, except for those with ultrathin oxides (<40 Å).

Measurement and numerical modeling of short-channel MOSFET gate capacitances

The gate-to-source and gate-to-drain capacitance of long-and short-channel n-MOSFETs have been measured and simulated using a two-dimensional numerical simulator that allows different inversion layer carrier mobility models to be used. Comparison of the experimental and simulated data indicates velocity saturation effect is seen in the capacitance data of the short-channel devices. Transverse-field dependence of the mobility is also found to be necessary to account for the experimental data.

Characterization of charge trapping in submicrometer NMOSFET's by gate capacitance measurements

Trapping of net positive charge at low gate stress voltage, and of net negative charge at high gate stress voltage, is observed through changes in the gate-to-drain capacitance of the stressed junction. These observations can be explained in terms of electron trapping, hole trapping, and generation of acceptor-like interface states located in the upper half of the bandgap. Channel shortening is also observed and found to exhibit a logarithmic time dependence.<<ETX>>

Extraction of MOSFET threshold voltage, series resistance, effective channel length, and inversion layer mobility from small-signal channel conductance measurement

This paper proposes and demonstrates the extraction of MOSFET threshold voltage, source-drain resistance, gate field mobility reduction factor, and transistor gain factor from the measurement of the small-signal source-drain conductance of a transistor as a function of dc gate bias with zero dc drain bias. The theory is based on the analytical model that includes the effects of source-drain resistance and gate-induced mobility reduction. It is shown that, by measuring devices of different drawn gate lengths, effective channel lengths and actual mobility can also be extracted. The results obtained are compared with those obtained by other measurement methods.

A new method of threshold voltage extraction via MOSFET gate-to-substrate capacitance measurement

A new method to extract MOSFET threshold voltage V/sub T/ by measurement of the gate-to-substrate capacitance C/sub gb/ of the transistor is presented. Unlike existing extraction methods based on I-V data, the measurement of C/sub gb/ does not require DC drain current to flow between drain nd source thus eliminating the effects of source and drain series resistance R/sub S/D/ , and at the same time, retains a symmetrical potential profile across the channel. Experimental and simulation results on devices with different sizes are presented to justify the proposed method.