N. Kistler

Mobility-field behavior of fully depleted SOI MOSFET's

This work reports measured effective mobility vs. effective vertical electric field and the accompanying experimental method of extraction for the fully depleted (FD) SOI MOSFET. The effective channel mobility vs. effective vertical electric field behavior was investigated as a function of the SOI film doping concentration, the SOI back-gate bias, and the SOI film thickness. The validity of using the approximation, Q/sub i/=C/sub ox/(V/sub GS//spl minus/V/sub TH/), for the inversion charge density in FD SOI is examined and experimentally confirmed.<<ETX>>

Modeling the I-V characteristics of fully depleted submicrometer SOI MOSFET's

In this paper, an analytic current-voltage model for submicrometer fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs is presented. This model takes into account the source/drain series resistances which can be especially high in thin film SOI devices. The effect of drain induced conductivity enhancement is also included, which is important for submicrometer channels. The model is verified by comparison to measured SOI I-V characteristics. Good agreement is obtained for SOI film thicknesses ranging from 40 to 220 nm and effective channel lengths down to 0.25 /spl mu/m.<<ETX>>

Sub-quarter-micrometer CMOS on ultrathin (400 AA) SOI

MOS transistors with effective channel lengths down to 0.2 mu m have been fabricated in fully depleted, ultrathin (400 AA) silicon-on-insulator (SOI) films. These devices do not exhibit punchthrough, even for the smallest channel lengths, and have performance characteristics comparable to deep-submicrometer bulk transistors. The NMOS devices have a p/sup +/-polysilicon gate, and the PMOS devices have an n/sup +/-polysilicon gate, giving threshold voltages close to 1 V with very light channel doping. Because the series resistance associated with the source and drain regions can be very high in such thin SOI films, a titanium salicide process was used using a 0.25 mu m oxide spacer. With this process, the sheet resistance of the silicided SOI layer is approximately 5 Omega / Square Operator . However, the devices still exhibit significant series resistance, which is likely due to contact resistance between the silicide and silicon source/drain regions.<<ETX>>

Symmetric CMOS in fully-depleted silicon-on-insulator using P/sup +/-polycrystalline SiGe gate electrodes

In this work, polycrystalline SiGe gate electrodes have been implemented on fully-depleted silicon-on-insulator with light channel doping. Symmetric NMOS and PMOS operation is achieved, with threshold voltages in the range of 0.4-0.6 V. The devices exhibit good short-channel behavior and near-ideal subthreshold slope. CMOS ring oscillators with enhancement-mode NMOS and PMOS have been fabricated, exhibiting propagation delays comparable to previously reported values for fully-depleted SOI.<<ETX>>

Detailed characterization and analysis of the breakdown voltage in fully depleted SOI n-MOSFET's

The breakdown voltage in fully depleted SOI n-MOSFETs has been studied over a wide range of film thicknesses, channel dopings, and channel lengths. In lightly-doped films, the breakdown voltage roll-off at shorter channel lengths becomes much less severe as the film thickness is reduced. This is a result of improved resistance to punchthrough and DIBL effects in thinner SOI. Consequently, at channel lengths below about 0.8 /spl mu/m, ultrathin (50 nm) SOI can provide better breakdown voltages than thicker films. At heavier doping levels the punchthrough and DIBL are suppressed, and there is little dependence of breakdown voltage on film thickness. Two-dimensional simulations have been used to investigate the breakdown behavior in these devices. It is found that the drain-induced barrier lowering affects the breakdown voltage both directly, via punchthrough, and indirectly through its effect on the current flow and hole generation in the high-field regions. >

Threshold voltage instability at low temperatures in partially depleted thin film SOI MOSFETs

The threshold voltage instability at low temperatures due to the floating Si film in partially depleted SIMOX was examined at low temperatures under normal operating conditions. Floating-film SOI MOS transistors suffer an accumulation of holes generated by impact ionization near the drain, at the lower Si film interface. As the potential at this interface increases due to hole accumulation, the source junction becomes forward biased, limiting the amount of charge which can accumulate. This causes the saturation kink effect. The increase in potential at the lower interface acts analogously to a positive bias in bulk devices and effectively decreases the threshold voltage of the device. The use of the channel contact alleviates the hole accumulation effect by providing a conducting path for the generated holes. Hence, the grounded film exhibits a higher threshold voltage than the floating film.<<ETX>>

Threshold voltage instability at low temperatures in partially depleted thin-film SOI MOSFETs

A threshold voltage instability phenomenon at low temperatures in partially depleted thin-film silicon-on-insulator (SOI) SIMOX (separation by implantation of oxygen) MOSFETs is reported. This phenomenon was investigated under normal MOSFET operating conditions for temperatures ranging from 300 K down to 10 K, with both the magnitude and duration of the instability observed to be strongly dependent on temperature. Threshold voltage shifts as small as 0 V at room temperature and as large as 0.29 V at 10 K are reported. The duration of the instability ranged in the tens of minutes and was observed to increase as the temperature was decreased.<<ETX>>

Scaling behavior of sub-micron MOSFETs on fully depleted SOI

Abstract Fully depleted silicon-on-insulator (SOI) MOSFETs offer a number of advantages over conventional bulk silicon transistors, making them attractive candidates for deep sub-micron low power electronics. In this paper, we present detailed characterization and analysis of the scaling behavior of fully depleted SOI MOSFETs down to quarter-micrometer channel lengths. Based on the consideration of transconductance, short channel effects, sub-threshold conduction and breakdown voltage, a scaling guideline for thin SOI devices is developed for 0.5 and 0.25 μm channel lengths in terms of silicon film thickness, channel doping, and channel length.

Monitoring the Electrical Properties of the Back Silicon Interface of Silicon-on-Sapphire Wafers

The density and the electrical nature of the interface traps at the silicon-sapphire interface of silicon-on-sapphire (SOS) MOSFETs have a significant influence on the electrical characteristics of these transistors. This letter describes a simple MOS test structure for evaluating the electrical properties of this interface of SOS wafers. Measurement and modeling of the C-V characteristics of the test structure fabricated on production SOS wafers are presented. We have demonstrated that the C-V characteristics are an efficient tool for studying the depletion of the silicon-sapphire interface by the interface trapped charge.

Substrate current measurements in thin SOI MOSFET's at 300 and 77 K

Measurements of impact-ionized hole current in fully depleted SOI (silicon-on-insulator) MOSFETs at room temperature and liquid nitrogen temperature are reported. The measured current exhibits properties similar to those of the substrate current in bulk transistors, except for higher drain biases when the parasitic bipolar in the device is significant. Since the body contact is effective in collecting only a small fraction of the total generated hole current, the body contact cannot be used to eliminate the bipolar action in thin SOI, at least for channel widths on the order of 10 mu m. >