Tadayoshi Enomoto

A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM

A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI has been developed using a 0.8- mu m triple-layer-Al, CMOS fabrication technology. A 13.02*12.51-mm/sup 2/ chip contains a specially developed 160-kb content addressable memory (CAM) and cellular automation processor (CAP). A single DISP chip can store a maximum of 2048 words, and performs dictionary search in various search modes, including an approximate word search. The character input rate for the dictionary search operation is 33 million characters per second. The DISP typically consumes 800 mW at a supply voltage of 5 V. A high-speed, functional 50000 word dictionary search system can be built with 25 DISP chips arranged in parallel, to play an important role in natural language processing. >

250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI

A 250-MHz, 16-b, fixed-point, super-high-speed video signal processor (S-VSP) ULSI has been developed for constructing a video teleconferencing system. Two major technologies have been developed. One is a high-speed large-capacity on-chip memory architecture that achieves both 250-MHz internal signal processing and 13.5-MHz input and output buffering. The other is a circuit technology that achieves 250-MHz operations with a convolver/multiplier, an arithmetic logic unit (ALU), an accumulator, and various kinds of static RAMs (SRAMs). A phase-locked loop (PLL) is also integrated to generate a 250-MHz internal clock. The S-VSP ULSI, which was fabricated with 0.8- mu m BiCMOS and triple-level-metallization technology, has a 15.5-mm*13.0-mm area and contains about 1.13 million transistors. It consumes 7 W at 250-MHz internal clock frequency with a single 5-V power supply. >

A real-time video signal processor suitable for motion picture coding applications

A real-time video signal processor (VSP) system has been developed. The system employs three multiprocessor clusters, each of which has 12 video signal processor modules (VSPMs). A VSPM in a cluster processes its assigned subimage by using an overlap-save technique. Each cluster uses the same multiprocessor structure, in which homogeneous processor modules are connected to input, output, and feedback buses in parallel and two bus switch units. By controlling these units, the clusters can be combined in pipeline and/or parallel forms. Each cluster also uses a variable delay unit which achieves up to one frame delay on the feedback bus. By using this unit, interframe processing can be carried out without using internal data memories in VSPMs for the frame delay. The employment of the bus switches and the variable delay unit increases flexibility for a variety of signal processing algorithms. The system performs 500 million operations per second and is currently used as a real-time evaluation system for low-bit-rate picture encoders. >

A microprogrammable real-time video signal processor (VSP) for motion compensation

A video signal processor (VSP) LSI circuit with a three pipelined architecture has been developed for pattern matching, which is fundamental for the motion compensation necessary for teleconferencing systems. A high-speed arithmetic logic unit with absolute-value calculation capability and a minimum/maximum value detector, which are essential to pattern matching, have been integrated on the VSP LSI. The chip was fabricated with a 2.5- mu m CMOS and double-layer metallization technology. The number of MOSFETs integrated on the 9.91*9.50-mm/sup 2/ chip is about 48000. It operates at a 14.3-MHz clock frequency with a single 5-V power supply and typically consumes 240 mW. An experimental video signal processing system, using a single VSP LSI chip, is discussed. >

A microprogrammable real-time video signal processor (VSP) LSI

A microprogrammable real-time video signal processor (VSP) LSI has been developed for constructing a parallel video signal processing system. The VSP LSI employs a flexible multistage pipelined architecture and can handle such sophisticated image signal processing as high-speed edge detection and motion compensation. It contains many operational function units such as an arithmetic logic unit and with absolute value calculation capability, a minimum/maximum value detector, a two-port SRAM, RAM address pointer and clocked bus lines. The VSP LSI has been designed using two different kinds of automatic layout programs. The chip, which was fabricated with a 2.5-/spl mu/m CMOS and double-layer metallization technology, has an area of 9.91/spl times/9.50 mm/SUP 2/ and contains about 48000 MOSFETs. It operates at a clock frequency of 14.3 MHz with a single 5-V power supply and typically consumes 240 mW. An experimental system, using a single VSP LSI chip, has been constructed in order to demonstrate various application capabilities, such as interframe difference operations, high-speed edge detection and motion compensation.

Monolithic analog adaptive equalizer integrated circuit for wide-band digital communication networks

This equaliser is presented with particular emphasis on architecture and performance. To reduce the size, cost, and power dissipation, and to improve the operation speed and performance, this equalizer IC employs many techniques such as all analog signal processing with parallel updating the weights and eliminating the offset according to the least mean-square algorithm, MOS VLSI fabrication process and switched capacitor technique. As the key building blocks, low- and high-speed MOS operational amplifiers and four-quadrant analog multipliers are specially developed. The 16 mm/SUP 2/ chip providing 5 taps operates on /spl plusmn/5 and 10 V power supplies with power dissipation of 570 mW. The maximum data rate is more than 200 kHz. For the linear adaptive equalizer configuration operating at a data rate of 100 kHz, the residual RMS distortion and convergence time are measured to be -40 dB and about 2 ms (200 iterations), respectively, when a binary signal with an initial RMS distortion of 40 percent (-7.96 dB) is applied.

A 300-MHz 16-b BiCMOS video signal processor

A 300-MHz 16-b full-programmable parallel-pipelined video signal processor ULSI has been developed. With multifunctional arithmetic units to achieve parallel vector processing, and with a phase-locked-loop (PLL) type clock generator to help attain the 300-MHz internal operating speed, this ULSI is able to attain, with only one chip, 30-frame-per-second full-CIF video data coding based on CCITT H.261. Two different types of pass-transistor BinMOS circuits have been developed to help achieve an access time of 3 ns for a 146-kb SRAM and for data buses. Fabricated with a 0.5- mu m BiCMOS and triple-layer metallization process technology, the video signal processor ULSI contains 1.27-million transistors in a 16.5*17.0-mm/sup 2/ die area. >

A programmable clock generator with 50 to 350 MHz lock range for video signal processors

Using 0.5-/spl mu/m CMOS triple-layer Al technology, a programmable clock generator based on a PLL (phase-locked loop) circuit has been developed for use as an on-chip clock generator in a 300-MHz video signal processor. It generates an internal clock whose frequency is an integral multiple of an external clock frequency, and its oscillating frequency ranges from 50 to 350 MHz. Experimental results show that the clock generator generates a 297-MHz clock with jitter reduced to 180 ps with a 27-MHz input clock, and that it oscillates at up to 348 MHz with a 31.7-MHz input clock.

A realtime microprogrammable video signal LSI

A signal processor employing a 3-stage pipelined architecture for efficient realtime video operations, such as edge filtering, motion picture coding and motion compensation, will be reported. Chip incorporates a peak value detector allowing high-speed vector quantization and pattern matching operation. The chip (94.5mm2) uses a 2.5μ CMOS double layer metal process and operates at 14.3MHz.

A 2.4-ns, 16-bit, 0.5-/spl mu/m CMOS arithmetic logic unit for microprogrammable video signal processor LSIs

A 16-b arithmetic logic unit (ALU) has been developed for achieving high-speed microprogrammable video signal processor LSIs. The ALU employs a parallel architecture with newly developed high-speed circuit operations, including highly parallel addition, operand look-ahead overflow detection, and carry select zero-flag detection. The unit contains 6,272 transistors in a 1.50 mm /spl times/ 1.09 mm die area using 0.5-/spl mu/m CMOS process technology, and 2.4-ns ALU operations have been successfully achieved.