Masaaki Yasumoto

Monolithic analog adaptive equalizer integrated circuit for wide-band digital communication networks

This equaliser is presented with particular emphasis on architecture and performance. To reduce the size, cost, and power dissipation, and to improve the operation speed and performance, this equalizer IC employs many techniques such as all analog signal processing with parallel updating the weights and eliminating the offset according to the least mean-square algorithm, MOS VLSI fabrication process and switched capacitor technique. As the key building blocks, low- and high-speed MOS operational amplifiers and four-quadrant analog multipliers are specially developed. The 16 mm/SUP 2/ chip providing 5 taps operates on /spl plusmn/5 and 10 V power supplies with power dissipation of 570 mW. The maximum data rate is more than 200 kHz. For the linear adaptive equalizer configuration operating at a data rate of 100 kHz, the residual RMS distortion and convergence time are measured to be -40 dB and about 2 ms (200 iterations), respectively, when a binary signal with an initial RMS distortion of 40 percent (-7.96 dB) is applied.

Single-Chip Adaptive Transversal Filter IC Employing Switched Capacitor Technology

Development of compact, high-speed, and low power adaptive transversal filters (ATFs) has been of great interest. Such ATFs have already been successfully fabricated in monolithic form employing a short channel MOSFET process and switched capacitor technique, using only complete analog circuit technology while eliminating inherent analog problems. This IC with five taps works with both ±5 V and 10 V supplies at a clock rate of more than 250 kHz. It has been designed for multipurpose applications such as a decision feedback equalizer (DFE), echo canceller (EC), and linear equalizer (LE), the last of which has already been reported [5]. The architecture to realize these applications will be described first. Much discussion is presented on the investigation of the operation, characteristics, and performance limitations of this IC in the DFE mode, from which those in the EC mode for two-wire full-duplex data transmission can be understood. For a single echo with magnitude of one half that of the original signal and delay time of one clock period from the original signal, and convergence factor of 0.2 for weight adaptation, the DFE operating at the clock rate of 100 kHz completes equalization within about 1.2 ms resulting in a residual rms distortion of -45.4 dB. The dominant performance limitation factors are found to be both the correlator harmonic distortion and transversal filter noise, but not the convolver harmonic distortion which is the dominant factor for the LE.

Promissing new fabrication process developed for stacked LSI's

A stacked CMOS LSI fabrication process has been developed for the purpose of realizing a short fabrication turn-around time, high fabrication yield and high integration density. This process consists of, in addition to the conventional LSI process, fabrication of vertical interconnections, surface planarization and thermal compression to obtain electrical interconnections between 2 layers. A 2-layer, bulk/CMOS ring oscillator consisting of p-channel MOSFETs on the upper layer and n-channel MOSFETs on the lower layer has been made using this new fabrication process. It has 31 bulk/CMOS inverter stages, each of which contains a single Au vertical interconnection with area of 10 × 10 µm2. A typical propagation delay time per stage for this device is measured to be 1.86 nsec at a supply voltage of 5 V.

Design, fabrication, and performance of scaled analog ICs

This paper concerns scaled MOS circuits for high-speed and high-density analog LSIs. The effect of scaling the devices employing three different scaling laws (constant electric field, constant voltage, and quasiconstant voltage laws) is examined using both the first-order approximation and two-dimensional device simulator. Versatile scaling relationships for analog circuits are then developed. They show that the bandwidth, transient response, and low-frequency gain are generally improved; however, the signal-to-noise ratio (S/N) is reduced by a scaling factor of k/SUP 0.5/ or k depending on which scaling law is used. To further investigate the scaling effects, scaled NMOS op amps are developed based mainly on the quasi-constant voltage law with k of approximately 2 and 3 compared to the conventional 8.5 /spl mu/m rule NMOS op amp. Improvements in slew rates and gain-bandwidth products are more than sixfold while keeping the low-frequency open-loop gain, power dissipation, and S/N almost unchanged.

Integrated CCD transversal filter matched to a pair of 16-bit complementary series

An integrated filter matched to a pair of 16-bit complementary series was fabricated employing four buried channel CCDs with parallel-in/serial-out approach for high speed operation. This letter presents the structure and operation of the filter and demonstrates various advantages, such as negligible deviation (0.016%) from expected signal-to-noise power gain, high peak-to-sidelobe ratio

Monolithic minimum phase CCD channel filter for a PCM codec employing overlapping-double-split-electrode technique

A monolithic CCD channel filter consisting of transmit-and-receive filters for a PCM codec was fabricated using a triple-layer polysilicon gate and NMOST process. This filter employed both a minimum phase design with a greatly reduced number of taps and newly developed overlapping-double-split-electrode (ODSE) structure in order to minimize chip area and eliminate excess capacitances at all of the sensing nodes. Improved filter performance, such as negligible degradation in frequency response, reduced power dissipation, a significantly small common mode signal, and consequently, much improved signal-to-noise ratio are discussed. Frequency responses, harmonic contents, and noise spectral densities are presented as experimental results. Signal-to-noise ratio was measured to be 84 dB with a total harmonic distortion of less than 0.4 percent.