Yukinori Ono

Ultimately thin double-gate SOI MOSFETs

The operation of 1-3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mode (for either front or back channel), is systematically analyzed. Strong interface coupling and threshold voltage variation, a large influence of substrate depletion underneath the buried oxide, the absence of drain current transients, and degradation in electron mobility are typical effects in these ultra-thin MOSFETs. The comparison of SG and DG configurations demonstrates the superiority of DG-MOSFETs: ideal subthreshold swing and remarkably improved transconductance (consistently higher than twice the value in SG-MOSFETs). The experimental data and the difference between SG and DG modes is explained by combining classical models with quantum calculations. The key effect in ultimately thin DG-MOSFETs is volume inversion, which primarily leads to an improvement in mobility, whereas the total inversion charge is only marginally modified.

Manipulation and detection of single electrons for future information processing

The ultimate goal of future information processing might be the realization of a circuit in which one bit is represented by a single electron. Such a challenging circuit would comprise elemental devices whose tasks are to drag, transfer, and detect single electrons. In achieving these tasks, the Coulomb blockade, which occurs in tiny conducting materials, plays an important role. This paper describes the current status of research on such single-charge-control devices from the viewpoints of circuit applications.

Fabrication method for IC-oriented Si single-electron transistors

A new fabrication method for Si single-electron transistors (SETs) is proposed. The method applies thermal oxidation to a Si wire with a fine trench across it on a silicon-on-insulator substrate. During the oxidation, the Si wire with the fine trench is converted, in a self-organized manner, into a twin SET structure with two single-electron islands, one along each edge of the trench, due to position-dependent oxidation-rate modulation caused by stress accumulation. Test devices demonstrated, at 40 K, that the twin SET structure can operate as two individual SETs. Since the present method produces two SETs at the same time in a tiny area, it is suitable for integrating logic circuits based on pass-transistor type logic and CMOS-type logic, which promises to lead to the fabrication of single-electron logic LSIs.

Nanoampere charge pump by single-electron ratchet using silicon nanowire metal-oxide-semiconductor field-effect transistor

Nanoampere single-electron pumping is presented at 20K using a single-electron ratchet comprising silicon nanowire metal-oxide-semiconductor field-effect transistors. The ratchet features an asymmetric potential with a pocket that captures single electrons from the source and ejects them to the drain. Directional single-electron transfer is achieved by applying one ac signal with the frequency up to 2.3GHz. We find anomalous shapes of current steps which can be ascribed to nonadiabatic electron capture.

Si complementary single-electron inverter with voltage gain

A Si complementary single-electron inverter in which two identical single-electron transistors (SETs) are packed is fabricated on a silicon-on-insulator substrate. For the fabrication, the vertical pattern-dependent oxidation method, which enables the formation of two tiny SETs aligned in parallel, is modified so that the two SETs can be connected in series to realize an inverter configuration. The resultant circuit occupies a very small area: 100×100 nm for each SET. For complementary operation, the electrical characteristics of one of the SETs are shifted using a side gate situated near the SET. Input–output transfer with a voltage gain larger than unity is demonstrated at 27 K.

Pauli-spin-blockade transport through a silicon double quantum dot

We present measurements of resonant tunneling through discrete energy levels of a silicon double quantum dot formed in a thin silicon-on-insulator layer. In the absence of piezoelectric phonon coupling, spontaneous phonon emission with deformation-potential coupling accounts for inelastic tunneling through the ground states of the two dots. Such transport measurements enable us to observe a Pauli spin blockade due to effective two-electron spin-triplet correlations, evident in a distinct bias-polarity dependence of resonant tunneling through the ground states. The blockade is lifted by the excited-state resonance by virtue of efficient phonon emission between the ground states. Our experiment demonstrates considerable potential for investigating silicon-based spin dynamics and spin-based quantum information processing.

Conductance modulation by individual acceptors in Si nanoscale field-effect transistors

The authors measured low-temperature (6–28K) conductance in nanoscale p-channel field-effect transistors lightly doped with boron. They observed a conductance modulation, which they ascribed to the trapping/detrapping of single holes by/from individual acceptors. The statistics of the appearance of the modulation in a few ten samples indicates that the number of acceptors is small, or even just one, suggesting that what the authors have observed is single-charge-transistor operation by a single-acceptor quantum dot.

Current quantization due to single-electron transfer in Si-wire charge-coupled devices

We observe a quantized current due to single-electron transfer in a small charge-coupled device, which consists of a narrow Si-wire channel with fine gates; the gate is used to form a tunable barrier potential. By modulating two barrier potentials under the fine gates with phase-shifted pulse voltages, quantized numbers of electrons are injected into and extracted from the charge island sandwiched by the two barriers. Current plateaus due to single-electron transfer are clearly observed at 20 K with frequencies up to 100 MHz and a current level of 16 pA.

Fabrication of Si single-electron transistors with precise dimensions by electron-beam nanolithography

Determining the relationship between wire size and the electrical characteristics of a single-electron transistor (SET) can significantly shorten the development time required to make SETs practical devices. In this study, this relationship was examined by fabricating SETs with precise dimensions using electron-beam nanolithography. The high-resolution resist HSQ provided fine wire patterns with small linewidth fluctuations. Si nanowires were made by etching using HSQ patterns as a mask, and then oxidized to produce SETs. The electrical characteristics were measured to determine the wire size required for making operational SETs. First, it was found that more oxidation widens the range of wire widths for which clear Coulomb blockade oscillations are observed. This is probably because more oxidation produces more oxidation-induced stress, which deepens the potential well essential for SET operation. In addition, it was experimentally confirmed that the gate capacitance is proportional to the nanowire lengt...

Room-temperature-operating data processing circuit based on single-electron transfer and detection with metal-oxide-semiconductor field-effect transistor technology

A single-electron-based circuit, in which electrons are transferred one by one with a turnstile and subsequently detected with a high-charge-sensitivity electrometer, was fabricated on a silicon-on-insulator substrate. The turnstile, which is operated by opening and closing two metal-oxide-semiconductor field-effect transistors alternately, allows single-electron transfer at room temperature owing to electric-field-assisted shrinkage of the single-electron box. It also achieves fast single-electron transfer (less than 10ns) and extremely long retention (more than 104s). We have applied these features to a multilevel memory and a time-division weighted sum circuit for a digital-to-analog converter.