Hiroshi Kotaki

Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS

We have developed a high speed dynamic threshold voltage MOSFET named B-DTMOS for ultra low power operation. This was realized using a bulk wafer containing an individual trench isolated shallow-well with a high concentration buried layer sandwiched between two low concentration layers surrounded by a deep well. The B-DTMOS achieved an excellent propagation delay time of 83.6 psec at 0.6 V operation and 103.3 psec at 0.5 V operation. This was realized due to ultra low body resistance of the B-DTMOS.

Miniaturized microDMFC using silicon microsystems techniques: performances at low fuel flow rates

This paper reports the design, fabrication and characterization of high performance miniaturized micro direct methanol fuel cells (microDMFC) functioning at room temperature under a forced low input fuel flow rate (<10 µL min−1) fabricated using silicon microsystems techniques. A room temperature maximum power output of 12.5 mW cm−2 has been measured at a fuel flow rate of 5.52 µL min−1 for a fuel cell surface area as small as 0.3 cm2 (corresponding to a fuel use efficiency of 14.1% at 300 K). At a lower flow rate of 1.38 µL min−1, the fuel use efficiency rises to 20.1% although the power density falls to 4.3 mW cm−2. The study revealed that improved room temperature cell performances in terms of power density can be achieved at low flow rates (<10 µL min−1) by (i) reducing the fuel cell area and (ii) reducing the microchannel cross-section. The study also revealed that higher fuel use efficiencies are obtained at lower fuel flow rates. Fuel (methanol) for the anode and an oxidant (air) for the cathode are supplied via a compact serpentine network of micron-size microfluidic and gas microchannels; by using silicon microsystems techniques we also render the fuel cell compatible with other silicon technologies such as microelectronics and micro- and nanoelectromechanical systems (MEMS/NEMS).

Novel low capacitance sidewall elevated drain dynamic threshold voltage MOSFET (LCSED) for ultra low power dual gate CMOS technology

We have developed a novel high speed dynamic threshold voltage MOSFET named LCSED for ultra low power operation. This was realized using sidewall elevated drain. The LCSED achieved the following excellent characteristics as compared to the bulk-DTMOS which we proposed earlier: 60% reduced occupation area; 65% reduced junction capacitance; 67% reduced forward leakage current between shallow-well and source/drain; lower transistor series resistance; smaller short channel effect; higher drive current. These effects realize ultra low power high speed operation.

Novel Oxygen Free Titanium Silicidation (OFS) Processing for Low Resistance and Thermally Stable SALICIDE (Self-Aligned Silicide) in Deep Submicron Dual Gate CMOS (Complementary Metal-Oxide Semiconductors)

A low resistance and thermally stable TiSi 2 self aligned silicide (SALICIDE) for deep submicron p + and n + dual gate complementary metal-oxide semiconductors (CMOS) has been developed. This was achieved through the use of a novel oxygen free silicidation (OFS) process using a reaction between a titanium included nitrogen (Ti x N y ) and an oxygen free poly-Si-gate. The oxygen free poly-Si was realized using low pressure chemical vapor deposition (LPCVD) system with nitrogen flow Load-Lock chamber. The OFS TiSi 2 film did not agglomerate after the treatment of the RTA at 1050°C for 20 s in a N 2 atmosphere and the additional furnace annealing at 900°C for 30 min. in a N 2 atmosphere. For both n + and p + gates, low sheet resistances (about 2.8 Ω/square.) were achieved under the 0.2 μm size

Elevated Polycide Source/Drain Shallow Junctions with Advanced Silicidation Processing and Al Plug/Collimated PVD (Physical Vapor Deposition)-Ti/TiN/Ti/Polycide Contact for Deep-Submicron Complementary Metal-Oxide Semiconductors

Low-resistivity shallow junctions and completely filled contact technologies have been developed. These were realized by forming the elevated polycide source/drain junction structure and Al plug/collimated PVD-Ti/TiN/Ti/Ti-polycide (APPOCIDE) contact structure through the use of advanced silicidation processes called AAS and BAS (arsenic ions doped into the polycide layer after silicidation and boron ions doped into the polycide layer after silicidation). About 2.0–2.1 Ω /square sheet resistances of n+-Ti-polycide and p+-Ti-polycide were reached at the same level as that of undoped Ti-polycide. Contact resistivities were 2–3×10-9 Ω cm2 for a 0.35-µm-diameter contact on both n+ and p+. These contact resistivities were two orders of magnitude lower than that of the conventional Al/TiN/Ti/n+ or p+-silicon structure. Furthermore, we proposed a unique consideration for the reasons for the relative difficulty in achieving silicidation with low sheet resistance of TiSi2 layer on n+- polysilicon as compared to that on undoped- polysilicon.

Direct tunneling N/sub 2/O gate oxynitrides for low-voltage operation of dual gate CMOSFETs

Dual gate CMOSFETs with high performance were successfully realized by using 2.8 nm N/sub 2/O-oxynitrides as gate dielectrics. Unlike other fabrication procedures, /sup 11/B/sup +/ ions instead of /sup 49/BF/sub 2//sup +/ were implanted into the gate electrodes of PMOSFETs. We demonstrated that boron diffusion through the 2.8 nm-oxynitrides is effectively blocked by the use of RTA. Substrate current due to hot-carrier effects was observed for NMOSFETs with T/sub ox/=2.8 nm and L=0.5 /spl mu/m even below 1 V. Gate-oxide leakage of surface-channel PMOSFETs is lower than that of NMOSFETs because of high barrier height for holes which significantly reduces hole direct tunneling compared with electron direct tunneling.

Electron Spin Resonance and Photoluminescence Study of Charge Trap Centers in Silicon Nitride Films and Fabrication of Proposed Oxide?Nitride?Oxide Sidewall 2-bit/Cell Nonvolatile Memories

We have proposed a novel oxide–nitride–oxide (ONO)-sidewall 2-bit/cell nonvolatile memory and fabricated 70-nm-node nonvolatile memory devices. For low-pressure chemical-vapor-deposition (LPCVD)-SiN films, with increasing SiH4/NH3 mixture gas ratio, we have found from ESR and PL evaluation that the paramagnetic defect density increases and some PL emission energy levels become deeper. We consider that the energy-level shift is due to the effects of trap potential overlapping, where the trap centers are generated at the excess silicon atoms in the SiN films. In this study, a SiH4/NH3 mixture gas ratio of less than 1:100 was used to suppress the potential overlapping. As a result, we have also shown that the proposed memory device has high performance and excellent scalability.

Epitaxial Silicon Growth by Load-Lock Low Pressure Chemical Vapor Deposition System for Elevated Source/Drain Formation

A silicon epitaxial layer on the active region of a Si substrate was selectively grown under a low temperature condition of 620°C with a low pressure chemical vapor deposition (LPCVD) employing SiH4 as a precursor, without high-temperature H2 annealing and ultra high vacuum chemical vapor deposition (UHV-CVD). This method was achieved by the use of a N2-purged wafer cassette and a load-lock chamber that was directly connected to the CVD chamber. A cross-sectional transmission electron microscopy (TEM) micrograph of the interface between the CVD-deposited film and the Si substrate revealed that the Si film was grown homoepitaxially, however nanometer-scaled silicon oxide islands were sparsely formed at the interface. Epitaxial film growth seemed to be achieved by lateral grain growth over oxide islands during film deposition. Polycrystalline Si was grown on the silicon oxide under the same deposition condition, and a Si epitaxial growth layer was formed on the active region selectively by wet chemical etching using HNO3, CH3COOH and HF-based solution. Since this system has higher throughput than conventional UHV-CVD or MBE systems, it is expected to become important for the development of future ULSI devices with a sub-50 nm-scale metal–oxide–semiconductor field effect transistor (MOSFET).

Negative-ion implantation into thin SiO2 layer for defined nanoparticle formation

Two methods to form nanoparticles at a certain depth in a thin oxide layer by negative-ion implantation into the oxide layer of silicon substrate have been investigated. One method is by implantation at a low energy and the other is by a thermal diffusion after implantation. Regarding the low-energy implantation, about 1keV of ion energy is required. In general, a surface charge-up of the oxide layer arises from a positive-ion implantation to affect ion penetration depth. In this research, we used negative ion implantation because of its advantage of almost “charge-up-free” feature, even for insulating materials. We obtained delta-layered gold nanoparticles (Au NPs) in a 25nm thick SiO2 layer on Si by the low-energy implantation method of gold negative ions at 1keV. The center depth and an average diameter of the delta-layered Au NPs were 5nm and 7nm, respectively. As by the thermal diffusion after implantation, silver negative ions were implanted into 25nm thick SiO2∕Si at 10keV with 5×1015ions∕cm2 at ro...

Fuel and CO 2 self-exchange system with micro fluid channels for a micro direct methanol fuel cell

This paper shows a self-exchange system to supply liquid fuel and to exhaust CO2 spontaneously for micro direct methanol fuel cell (muDMFC). The system performs effectively and continuously without any circulation loops and external pumps. The fuel is carried to the anode due to capillary force. The system is consisted of a hydrophobic porous membrane and two comb-shape channels. It was confirmed that the muDMFC works with a less differential pressure than1 kPa between a fuel inlet and a CO2 outlet. The fuel supply rate of only several mul/min/cm2 was needed for the DMFC to work. Furthermore, the fuel supply rate was spontaneously varied along the electric current with constant pressure.