Seizo Kakimoto

Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS

We have developed a high speed dynamic threshold voltage MOSFET named B-DTMOS for ultra low power operation. This was realized using a bulk wafer containing an individual trench isolated shallow-well with a high concentration buried layer sandwiched between two low concentration layers surrounded by a deep well. The B-DTMOS achieved an excellent propagation delay time of 83.6 psec at 0.6 V operation and 103.3 psec at 0.5 V operation. This was realized due to ultra low body resistance of the B-DTMOS.

MOCVD Growth of InP on 4-inch Si Substrate with GaAs Intermediate Layer

This letter describes the heteroepitaxy of InP on Si by MOCVD. A new epitaxial structure with a thin GaAs intermediate layer (InP/GaAs/Si) is proposed to alleviate the large lattice mismatch (8.4%) between InP and Si. Using this structure, a 4-inch InP single crystal with a mirror-like surface and good thickness uniformity (Δd/d=±10%) was obtained. Residual stress in the InP film was 5.7±108 dyn/ cm2 for the InP/GaAs/Si structure, as compared to 8.3×108 dyn/cm2 for the InP directly grown on Si. This shows that the GaAs intermediate layer is also effective in reducing the residual stress in the InP epilayer.

Novel low capacitance sidewall elevated drain dynamic threshold voltage MOSFET (LCSED) for ultra low power dual gate CMOS technology

We have developed a novel high speed dynamic threshold voltage MOSFET named LCSED for ultra low power operation. This was realized using sidewall elevated drain. The LCSED achieved the following excellent characteristics as compared to the bulk-DTMOS which we proposed earlier: 60% reduced occupation area; 65% reduced junction capacitance; 67% reduced forward leakage current between shallow-well and source/drain; lower transistor series resistance; smaller short channel effect; higher drive current. These effects realize ultra low power high speed operation.

Seeded Electron Beam Recrystallization of Large Area SOI Using Striped Tungsten Encapsulation Technique

Large area SOI (silicon on insulator) film with (001) orientation has been produced by applying a seeded electron beam recrystallization technique to the specimen with striped encapsulation. The encapsulation stripes consisted of tungsten and polysilicon. A pseudoline electron beam was scanned parallel to the stripes. A 400 µm×800 µm area had become a single crystal including subgrain boundaries in one sweep. These subgrain boundaries were confined to the region between the encapsulation stripes. The orientation of the crystal gradually rotates from (001)[110] to (103)[33] as recrystallization propagated away from the seed.

Direct tunneling N/sub 2/O gate oxynitrides for low-voltage operation of dual gate CMOSFETs

Dual gate CMOSFETs with high performance were successfully realized by using 2.8 nm N/sub 2/O-oxynitrides as gate dielectrics. Unlike other fabrication procedures, /sup 11/B/sup +/ ions instead of /sup 49/BF/sub 2//sup +/ were implanted into the gate electrodes of PMOSFETs. We demonstrated that boron diffusion through the 2.8 nm-oxynitrides is effectively blocked by the use of RTA. Substrate current due to hot-carrier effects was observed for NMOSFETs with T/sub ox/=2.8 nm and L=0.5 /spl mu/m even below 1 V. Gate-oxide leakage of surface-channel PMOSFETs is lower than that of NMOSFETs because of high barrier height for holes which significantly reduces hole direct tunneling compared with electron direct tunneling.

Study of an Elevated Drain Fabrication Method for Ultra-Shallow Junction

An elevated diffusion layer fabricated from polycrystalline silicon (poly-Si) by solid phase diffusion was investigated in detail by secondary-ion mass spectroscopy (SIMS) analysis. We clarified that it was necessary to control the native oxide in the poly-Si/Si substrate interface and use small-grained poly-Si to fabricate uniform and controllable shallow junctions. The low-capacitance sidewall-elevated drain (LCSED) metal oxide semiconductor field-effect transistor (MOSFET) fabricated by the oxygen-free load-lock low-pressure chemical vapor deposition (LPCVD) poly-Si (L/L poly-Si) was extremely effective for marked scaling down of transistor size and realizing an ultra low reversed junction leakage current.

Novel Nonvolatile Random-Access Memory with Si Nanocrystals for Ultralow-Power Scheme

A novel nonvolatile memory with Si nanocrystals has been developed. It has a floating gate consisting of a thin poly Si film and Si nanocrystals. It could be written or erased when a low voltage of +3 V or -3 V was supplied to the gate electrode. On the other hand, no hysteresis was observed at +1 V or -1 V. These characteristics enable the realization of a random-access memory that operates with extremely low power consumption. In this paper, a memory cell array suitable for novel memory devices is also described. The cell array features well bitline technology and the cell area is reduced to 4 F2 (F: feature size) by winding trench isolation. Applying the novel device to the cell array enables realization of high-density, random-access, nondestructive readout and ultralow-power memories.

Influence of N2O Oxynitridation on Interface Trap Generation in Surface-Channel p-Channel Metal Oxide Semiconductor Field Effect Transistors

The influence of N 2 O oxynitridation on hot-carrier-induced degradation of surface-channel p-channel metal oxide semiconductor field effect transistors was investigated. N 2 O oxynitridation reduces electron trapping due to the high barrier height for electron injection. N 2 O oxynitridation has little effect on electron and hole energies for interface trap creation. For drain avalanche hot electron injection, the role of a nitrogen-rich region as the diffusion barrier of hydrogen species is to reduce interface trap generation by chemical reaction between hydrogen atoms and Si 3 =Si-H precursors at the Si/SiO 2 interface. However, interface trap generation is enhanced by the existence of nitrogen atoms near the Si/SiO 2 interface for channel hot hole injection. The enhancement of hole trapping may be due to a decrease in the compressive stress near the Si/SiO 2 interface by nitrogen incorporation.